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| Number | Title | Issue Date |
| 8041925 | Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least o... | 10/18/2011 |
| 8019970 | Three-dimensional networking design structure A design structure embodied in a machine readable medium used in a design process includes a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements; one or more networking layers disposed between the p... | 09/13/2011 |
| 8010771 | Communication system for controlling intercommunication among a plurality of communication nodes The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nod... | 08/30/2011 |
| 7991978 | Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execut... | 08/02/2011 |
| 7987339 | Processing system with interspersed processors and dynamic pathway creation A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of pro... | 07/26/2011 |
| 7987338 | Processing system with interspersed processors using shared memory of communication elements A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of pro... | 07/26/2011 |
| 7962716 | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The ... | 06/14/2011 |
| 7953956 | Reconfigurable circuit with a limitation on connection and method of determining functions of logic circuits in the reconfigurable circuit A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing c... | 05/31/2011 |
| 7937557 | System and method for intercommunication between computers in an array A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be c... | 05/03/2011 |
| 7937558 | Processing system with interspersed processors and communication elements A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of pro... | 05/03/2011 |
| 7886128 | Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimension A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify a... | 02/08/2011 |
| 7865695 | Reading and writing a memory element within a programmable processing element in a plurality of modes An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory ele... | 01/04/2011 |
| 7865694 | Three-dimensional networking structure A multi-layer silicon stack architecture includes one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each c... | 01/04/2011 |
| 7831801 | Direct memory access-based multi-processor array A direct memory access (“DMA”)-based multi-processor array architecture that may be implemented in a single integrated circuit is described. The integrated circuit includes a plurality of processing units. A first processing unit and a second processing unit of ... | 11/09/2010 |
| 7788466 | Integrated circuit with a plurality of communicating digital signal processors A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal ... | 08/31/2010 |
| 7788467 | Methods and apparatus for latency control in a multiprocessor system Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a p... | 08/31/2010 |
| 7788465 | Processing system including a reconfigurable channel infrastructure comprising a control chain with combination elements for each processing element and a programmable switch between each pair of neighboring processing elements for efficient clustering of processing elements A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as m... | 08/31/2010 |
| 7783861 | Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by selecting from inter-block and intra block transfers When an instruction code “MVLR” is sent from a control processor in a PE having a mask register MR in operation setting, when the direction register F is ON, if a counter and transfer result storing buffer T is ≧M, a value of T−M is stored in buffer T, and i... | 08/24/2010 |
| 7774579 | Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ... | 08/10/2010 |
| 7761687 | Ultrascalable petaflop parallel supercomputer A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes... | 07/20/2010 |
| 7650483 | Execution of instructions within a data processing apparatus having a plurality of processing units A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated o... | 01/19/2010 |
| 7636835 | Coupling data in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ... | 12/22/2009 |
| 7624250 | Heterogeneous multi-core processor having dedicated connections between processor cores The disclosure describes a processor having processor cores integrated on the same die that have different functional operationality. The processor also includes a chain of multiple dedicated unidirectional connections spanning processor cores. The multiple dedicate... | 11/24/2009 |
| 7590821 | Digital signal processing integrated circuit with I/O connections A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors (10). Configurable multiplexing circuits (12), are placed between IO connections (11a,b) and the I... | 09/15/2009 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing s... | 04/28/2009 |
| 7454593 | Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in th... | 11/18/2008 |
| 7444276 | Hardware acceleration system for logic simulation using shift register as local cache A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. E... | 10/28/2008 |
| 7418536 | Processor having systolic array pipeline for processing data packets A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of progr... | 08/26/2008 |
| 7406582 | Resolving crossing requests in multi-node configurations A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other no... | 07/29/2008 |
| 7406075 | Crossbar switch, method for controlling operation thereof, and program for controlling operation thereof A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch circuit receives from a node of a previous stage a designated address t... | 07/29/2008 |
| 7386689 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circui... | 06/10/2008 |
| 7383242 | Computer-implemented method and apparatus for item processing A method and apparatus for item processing is disclosed which provides a stand alone clearing solution having an imaged enable environment for item processing and balancing. The present invention incorporates user-definable balancing control rules, balancing control... | 06/03/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370170 | Data mask as write-training feedback flag Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is conver... | 05/06/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366580 | Production line control using shift registers for contact lens manufacture A method for controlling a production line for the manufacture and/or packaging of contact lenses which production line simultaneous by processes at least two lots, the method comprising dividing at least a portion of the production line into a series of cells throu... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
