Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7650483 | Execution of instructions within a data processing apparatus having a plurality of processing units A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated o... | 01/19/2010 |
| 7636835 | Coupling data in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ... | 12/22/2009 |
| 7624250 | Heterogeneous multi-core processor having dedicated connections between processor cores The disclosure describes a processor having processor cores integrated on the same die that have different functional operationality. The processor also includes a chain of multiple dedicated unidirectional connections spanning processor cores. The multiple dedicate... | 11/24/2009 |
| 7590821 | Digital signal processing integrated circuit with I/O connections A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors (10). Configurable multiplexing circuits (12), are placed between IO connections (11a,b) and the I... | 09/15/2009 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing s... | 04/28/2009 |
| 7454593 | Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in th... | 11/18/2008 |
| 7444276 | Hardware acceleration system for logic simulation using shift register as local cache A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. E... | 10/28/2008 |
| 7418536 | Processor having systolic array pipeline for processing data packets A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of progr... | 08/26/2008 |
| 7406582 | Resolving crossing requests in multi-node configurations A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other no... | 07/29/2008 |
| 7406075 | Crossbar switch, method for controlling operation thereof, and program for controlling operation thereof A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch circuit receives from a node of a previous stage a designated address t... | 07/29/2008 |
| 7386689 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circui... | 06/10/2008 |
| 7383242 | Computer-implemented method and apparatus for item processing A method and apparatus for item processing is disclosed which provides a stand alone clearing solution having an imaged enable environment for item processing and balancing. The present invention incorporates user-definable balancing control rules, balancing control... | 06/03/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7370170 | Data mask as write-training feedback flag Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is conver... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366580 | Production line control using shift registers for contact lens manufacture A method for controlling a production line for the manufacture and/or packaging of contact lenses which production line simultaneous by processes at least two lots, the method comprising dividing at least a portion of the production line into a series of cells throu... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7360220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two di... | 04/15/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7356026 | Node translation and protection in a clustered multiprocessor system A method of node translation for communicating over virtual channels in a clustered multiprocessor system using connection descriptors (CDs), which specify the endpoint nodes for virtual connections. The system includes a local processing element node, a remote proc... | 04/08/2008 |
| 7356669 | Processing system and method for transmitting data A split protocol transmission method for transmitting data and a communication thread identifier for said data along a communication path from a source functional unit (SFU) to a destination functional unit (DFU) via zero or more intermediate functional units (IFU) ... | 04/08/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7349670 | Modular wireless test architecture and method A modular test chassis for use in testing wireless devices includes a backplane and a channel emulation module coupled to the backplane. The channel emulation module comprises circuitry for emulating the effects of a dynamic physical environment (including air, inte... | 03/25/2008 |
| 7343362 | Low complexity classification from a single unattended ground sensor node Disclosed are a system and method of multi-modality sensor data classification and fusion comprising partitioning data stored in a read only memory unit on a sensor node using a low query complexity boundary-decision classifier, applying an iterative two-dimensional... | 03/11/2008 |
| 7342414 | Fast router and hardware-assisted fast routing method A fast router and a fast hardware-assisted routing method are disclosed in a network having endpoints, switches and interconnect links. The switches are programmable to allow endpoints to be connected through a particular configuration of switches. The switches also... | 03/11/2008 |
| 7337249 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 02/26/2008 |
| 7334030 | Method and apparatus for the addition and removal of nodes from a common interconnect An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect i... | 02/19/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7330857 | Search engine with two-dimensional linearly scalable parallel architecture In a search engine with two-dimensional scalable architecture for searching of a collection of documents, the search engine comprises data processing units which forms set of nodes connected in a network, a first set of nodes comprising dispatch nodes, a second set ... | 02/12/2008 |
| 7324564 | Transmitting odd-sized packets over a double data rate link A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link... | 01/29/2008 |
| 7320056 | Multi-processor system Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus c... | 01/15/2008 |
| 7319669 | Method and system for controlling packet flow in networks A system and method for transmitting and bundling network packets is provided. The incoming network packet size is determined and if the remote buffer space is sufficient to hold the network packet it is transmitted to the destination port. If the remote buffer spac... | 01/15/2008 |
| 7318110 | Storage system, storage device and information common sharing method by utilizing storage device The storage device is provided with a synchronization controller to realize synchronization control of information for the other storage devices when information is updated. This synchronization controller is further provided with a synchronization level registratio... | 01/08/2008 |
| 7315934 | Data processor and program for processing a data matrix A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit... | 01/01/2008 |
| 7315267 | Mixed-mode semiconductor memory A mixed-mode semiconductor memory includes a memory bank array, an analog/digital converter, a digital/analog converter, a plurality of digital buses and a control unit. The memory bank array includes a plurality of memory banks that are each composed of a plurality... | 01/01/2008 |
| 7315923 | System and method for combining data streams in pipelined storage operations in a storage network Described herein are systems and methods for multiplexing pipelined data for backup operations. Various data streams are combined such as by multiplexing by a multiplexing module. The multiplexing module combines the data from the various data streams received by re... | 01/01/2008 |