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...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
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| Number | Title | Issue Date |
| 8078830 | Processor array accessing data in memory array coupled to output processor with feedback path to input sequencer for storing data in different pattern An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) ... | 12/13/2011 |
| 8078829 | Scaleable array of micro-engines for waveform processing A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting... | 12/13/2011 |
| 8078831 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data pref... | 12/13/2011 |
| 8060725 | Processor architecture with processing clusters providing vector and scalar data processing capability A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on accordi... | 11/15/2011 |
| 8055879 | Tracking network contention Methods, apparatus, and product for tracking network contention on links among compute nodes of an operational group in a point-to-point data communications network of a parallel computer are disclosed. In embodiments of the present invention, each compute node is c... | 11/08/2011 |
| 8055878 | Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by s... | 11/08/2011 |
| 8037283 | Multi-core stream processor having (N) processing units and (N+1) fetching units In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N≧2. When the scheduler receives a stream element from a Pth | 10/11/2011 |
| 7984266 | Integrated computer array with independent functional configurations A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be c... | 07/19/2011 |
| 7941634 | Array of processing elements with local registers Specialized image processing circuitry is usually implemented in hardware in a massively parallel way as a single instruction multiple data (SIMD) architecture. The invention prevents long and complicated connection paths between a processing element and the memory ... | 05/10/2011 |
| 7930517 | Programmable pipeline array An array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an ... | 04/19/2011 |
| 7925860 | Maximized memory throughput using cooperative thread arrays In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus processing may take relatively small amounts of time to compute as compared to memory accesses times required to r... | 04/12/2011 |
| 7853774 | Managing buffer storage in a parallel processing environment An integrated circuit including a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles; and memory coupled to the switch to ... | 12/14/2010 |
| 7802073 | Virtual core management The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores... | 09/21/2010 |
| 7797512 | Virtual core management A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system furth... | 09/14/2010 |
| 7793075 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 09/07/2010 |
| 7793074 | Directing data in a parallel processing environment An apparatus comprises a plurality of processor cores, and an interconnection network to route data among the processor cores based on destination information in the data. The processor cores are configured to forward the data to a final destination if the destinati... | 09/07/2010 |
| 7769980 | Parallel operation device allowing efficient parallel operational processing In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD ins... | 08/03/2010 |
| 7734894 | Managing data forwarded between processors in a parallel processing environment based on operations associated with instructions issued by the processors An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over da... | 06/08/2010 |
| 7725679 | Distributed arrays in parallel computing environments The present invention provides a method and system to implement a distributed array using the distributed property as an attribute attachable to an array. The present invention maintains the top level array implementation so as to avoid making the top level users to... | 05/25/2010 |
| 7725680 | Pipeline interposer An application specific integrated circuit (ASIC) comprises a first bus that communicates with inputs and outputs of N processing modules, where N is an integer greater than 1. A control module communicates with the first bus and a second bus that is different than ... | 05/25/2010 |
| 7694106 | Multiprocessor system A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command i... | 04/06/2010 |
| 7689808 | Data processor and data process method A data processor includes a reader for reading a bit stream stored in a storage if there is free space of 8 bits or more in a buffer and outputting to a first array changer, the first array changer for changing an array sequence of the 8 bits in reversed sequence fo... | 03/30/2010 |
| 7673117 | Operation apparatus An operation apparatus able to continuously perform processing involving computations differing according to the input conditions, able to keep down useless processing when for example the processing may be interrupted in the middle if certain conditions are satisfi... | 03/02/2010 |
| 7673118 | System and method for vector-parallel multiprocessor communication This present invention brings to the multiprocessor what vectorization brought to the single processor. It provides similar tools to speed communication that have traditionally been used to speed computation; namely, the capability to program optimal communication a... | 03/02/2010 |
| 7647472 | High speed and high throughput digital communications processor with efficient cooperation between programmable processing components An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue m... | 01/12/2010 |
| 7644254 | Routing data packets with hint bit for each six orthogonal directions in three dimensional torus computer system set to avoid nodes in problem list A method and apparatus for dynamically rerouting node processes on the compute nodes of a massively parallel computer system using hint bits to route around failed nodes or congested networks without restarting applications executing on the system. When a node has a... | 01/05/2010 |
| 7627736 | Thread manager to control an array of processing elements A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another. ... | 12/01/2009 |
| 7581079 | Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify a... | 08/25/2009 |
| 7577820 | Managing data in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over da... | 08/18/2009 |
| 7558943 | Processing unit for broadcast parallel processing A processing unit includes a control processor and a plurality of element processors having register files. At least two of the element processors pre-receive different parameters, store the parameter data in the register files, receive the same memory address and t... | 07/07/2009 |
| 7555630 | Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element. | 06/30/2009 |
| 7539845 | Coupling integrated circuits in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ... | 05/26/2009 |
| 7526630 | Parallel data processing apparatus A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit ope... | 04/28/2009 |
| 7523292 | Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction co... | 04/21/2009 |
| 7516300 | Active memory processing array topography and method An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logica... | 04/07/2009 |
| 7478222 | Programmable pipeline array Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an in... | 01/13/2009 |
| 7461235 | Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performan... | 12/02/2008 |
| 7461236 | Transferring data in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles according to a switch instruction indica... | 12/02/2008 |
| 7461234 | Loosely-biased heterogeneous reconfigurable arrays A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or... | 12/02/2008 |
| 7447872 | Inter-chip processor control plane communication An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane... | 11/04/2008 |
