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| Number | Title | Issue Date |
| 7949853 | Two dimensional addressing of a matrix-vector register array A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column h... | 05/24/2011 |
| RE42170 | Control of information processing using one or more peripheral apparatus At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which the information processing apparatus controls the peripheral apparatus ... | 02/22/2011 |
| 7809748 | Extended cell information in multidimensional data models Sharable extended cell information is used by multidimensional data models to enable cell annotations and line item details. Annotations are notes stored with a cell in a multidimensional dataset. Line item details permit levels of numeric detail below the lowest di... | 10/05/2010 |
| 7779228 | Quantum information processing device and method Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two energy states of at least four energy states, and transition energy betwe... | 08/17/2010 |
| 7739479 | Method for providing physics simulation data A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data. ... | 06/15/2010 |
| 7716454 | Method and apparatus for matrix decomposition in programmable logic devices A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation b... | 05/11/2010 |
| 7676646 | Packet processor with wide register set architecture A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is conf... | 03/09/2010 |
| 7571300 | Modular distributive arithmetic logic unit A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-w... | 08/04/2009 |
| 7437542 | Identifying and processing essential and non-essential code separately A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pi... | 10/14/2008 |
| 7437533 | Quantum information processing device and method Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two energy states of at least four energy states, and transition energy betwe... | 10/14/2008 |
| 7421689 | Processor-architecture for facilitating a virtual machine monitor Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present inventi... | 09/02/2008 |
| 7409500 | Systems and methods for employing speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requ... | 08/05/2008 |
| 7409503 | Register file systems and methods for employing speculative fills Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are ... | 08/05/2008 |
| 7404977 | Rennets The present invention describes an aspartic protease produced by a fungus from the class Eurotiomycetes, comprising the amino acid sequence of FDTGSSD or FDTGSSE. The present invention further provides a process for identifying new milk clotting enzymes comprising s... | 07/29/2008 |
| 7406565 | Multi-processor systems and methods for backup for non-coherent speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source r... | 07/29/2008 |
| 7395538 | Scalable packet processing systems and methods A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configure... | 07/01/2008 |
| 7395082 | Method and system for handling events in an application framework for a wireless device Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be deter... | 07/01/2008 |
| 7386619 | System and method for allocating communications to processors in a multiprocessor system In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. ... | 06/10/2008 |
| 7383409 | Cache systems and methods for employing speculative fills One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comp... | 06/03/2008 |
| 7376794 | Coherent signal in a multi-processor system Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the m... | 05/20/2008 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exis... | 05/13/2008 |
| 7373543 | Method and apparatus for uninterrupted packet transfer using replication over disjoint paths A method of operating a fault tolerant connection in a network is described. The network includes a number of network elements and a number of links. Each of the network elements is coupled to at least one other of the network elements by at least one of the links. ... | 05/13/2008 |
| 7370048 | File storage method and apparatus A method for storing data in a data storage area of a computer that utilizes hashing functions to avoid collision of data records. A first hash function attempts to place a new data record in a home address in the data table. If a data record already exists in that ... | 05/06/2008 |
| 7370156 | Unity parallel processing system and method Present invention unity parallel processing systems and methods facilitate flexible utilization of sequential program applications in a distributed multi-computer parallel processing environment. The new unity parallel processing architecture enables multiple proces... | 05/06/2008 |
| 7369683 | Imaging device In an imaging device of the present invention, an imaging element 2 is driven in a thinning read-out mode for reading out signal charges from a subset of pixels, or in an all-pixels read-out mode for reading out signal charges from all pixels. When the imagin... | 05/06/2008 |
| 7366304 | Cruable U-NII wireless radio with secure, integral antenna connection via SM BIOS in U-NII wireless ready device A method that utilizes software and hardware mechanisms to meet the FCC requirement for a U-NII antenna to be an integral part of the device in which it operates, while providing wireless ready U-NII devices and CRUable U-NII radios. Enhancements are made to the sof... | 04/29/2008 |
| 7363399 | Method, apparatus and computer program product providing storage network dynamic tuning of I/O flow with Queue Depth In accordance with a computer program product, apparatus and a method there is provided a redundant network wherein a host computer operates with a plurality of storage devices by monitoring conditions of the multipath storage network and controlling a storage multi... | 04/22/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7363398 | Intelligent total access system A system for interfacing a user with an electronic device. An accessor device provides a user interface matched to the needs, abilities and intentions of the user and translates the user input commands and data into commands for the electronic device. An intelligent... | 04/22/2008 |
| 7360218 | System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. ... | 04/15/2008 |
| 7360222 | Extensions to coupling channels to support multiple coupling facility sharing, interrupts, and message passing A method for use in a computer system for extending coupling channels through the addition of specific hardware interrupts and controls to allow 1) sharing of receiver resources among multiple Coupling Facility (CF) logical partitions (LPARs), 2) direct CEC to CEC m... | 04/15/2008 |
| 7360217 | Multi-threaded packet processing engine for stateful packet processing A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to acco... | 04/15/2008 |
| 7360203 | Program tracing in a multithreaded processor A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread I... | 04/15/2008 |
| 7356608 | System and method for implementing LAN within shared I/O subsystem A shared I/O subsystem for providing network protocol management for a plurality of computer systems. The shared I/O subsystem includes a plurality of I/O interfaces where each of the I/O interfaces operatively couples one of the computer systems to the shared I/O s... | 04/08/2008 |
| 7356735 | Providing support for single stepping a virtual machine in a virtual machine environment Methods and systems to provide support for single stepping a virtual machine in a virtual machine environment are disclosed. An exemplary method may include receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), det... | 04/08/2008 |
| 7356622 | Method and apparatus for managing and formatting metadata in an autonomous operation conducted by a third party An apparatus, system, and method for managing and formatting data in an autonomous data transfer operation are provided. An initialization module is configured to prepare metadata corresponding to a data source. A loader loads autonomous operation instructions corre... | 04/08/2008 |
| 7353474 | System and method for accessing signals of a user design in a programmable logic device Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of si... | 04/01/2008 |
| 7353311 | Method of accessing information and system therefor A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority am... | 04/01/2008 |
| 7353299 | Method and apparatus for managing autonomous third party data transfers An apparatus, system, and method for managing and formatting data in an autonomous data transfer operation are provided. An initialization module is configured to prepare metadata corresponding to a data source. A loader loads autonomous operation instructions corre... | 04/01/2008 |
