Class 711/5 - For multiple memory modules (e.g., banks, interleaved memory)

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter wherein logical addresses are determined
No. of patents: 1585
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190809	Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage locatio...	05/29/2012
8190808	Memory device having staggered memory operations A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. S...	05/29/2012
8151031	Local memories with permutation functionality for digital signal processors A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed ...	04/03/2012
8151030	Method of increasing DDR memory bandwidth in DDR SDRAM modules The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data bur...	04/03/2012
8135897	Memory architecture A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said bank...	03/13/2012
8127069	Memory device including self-ID information Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each ba...	02/28/2012
8103818	Memory module and auxiliary module for memory In a memory module 100, an address generating circuit 120, using the highest order bit of a row address output by a memory controller 12, will generate a highest order bit BA2 of a bank address insufficient for the purpose of identificati...	01/24/2012
8090896	Address generation for multiple access of memory A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order,...	01/03/2012
8086783	High availability memory system A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank i...	12/27/2011
8078791	Ordering refresh requests to memory A device may generate a refresh signal that identifies a beginning of a refresh interval, determine the availability of banks of a memory device, and send refresh requests to the banks during the refresh interval based on the availability of the banks. ...	12/13/2011
8074010	Intelligent memory banks for storing vectors An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell ...	12/06/2011
8051239	Multiple access for parallel turbo decoder A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first an...	11/01/2011
8032688	Micro-tile memory interfaces In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bi...	10/04/2011
8028257	Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm ...	09/27/2011
8019927	Electronic tag system having bank status and controlling method thereof An electronic tag system, an electronic tag, and a controlling method thereof according to the present invention include an electronic tag that includes a memory having a divided band and a bank status that stores a status of data stored in the divided bank, a contr...	09/13/2011
8006028	Enabling memory module slots in a computing system after a repair action Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slot...	08/23/2011
7996597	Mapping address bits to improve spread of banks A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perf...	08/09/2011
7979622	Memory access method A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive...	07/12/2011
7970980	Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data ...	06/28/2011
7966443	Memory systems including memory devices coupled together in a daisy-chained arrangement A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the mem...	06/21/2011
7966444	Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr...	06/21/2011
7934047	Memory module and memory system A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different ...	04/26/2011
7930465	Determining operation mode for semiconductor memory device A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad...	04/19/2011
7913030	Storage device with transaction logging capability In one aspect, a system for indexing transactions over a shared bus is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with the bus. Each of the storage devices is configured to store data....	03/22/2011
7873776	Multiple-core processor with support for multiple virtual processors A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and core/bank mapping logic coupled to the cache banks and processor cores. Duri...	01/18/2011
7870326	Multiprocessor system and method thereof A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first pr...	01/11/2011
7844771	System, method and storage medium for a memory subsystem command interface A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of ...	11/30/2010
7840744	Rank select operation between an XIO interface and a double data rate interface In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) de...	11/23/2010
7822910	Method of flexible memory segment assignment using a single chip select Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that ...	10/26/2010
7822911	Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory contr...	10/26/2010
7818488	Memory module with registers Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal i...	10/19/2010
7805561	Method and system for local memory addressing in single instruction, multiple data computer system A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight ...	09/28/2010
7793034	Memory controller and method for multi-path address translation in non-uniform memory configurations In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a ...	09/07/2010
RE41589	Memory system performing fast access to a memory location by omitting the transfer of a redundant address A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The proc...	08/24/2010
7779198	Method and apparatus of multiple abbreviations of interleaved addressing of paged memories An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B−1) each addressing more than one and less than all of the memory banks. The interleaves are offset...	08/17/2010
7774535	Memory system and memory device According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory device. The second memory device is configured to receive write data f...	08/10/2010
7752379	Managing write-to-read turnarounds in an early read after write memory system Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a s...	07/06/2010
7725641	Memory array structure and single instruction multiple data processor including the same and methods thereof A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data...	05/25/2010
7707351	Methods and systems for an identifier-based memory section A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a ...	04/27/2010
7685354	Multiple-core processor with flexible mapping of processor cores to cache banks A multiple-core processor providing flexible mapping of processor cores to cache banks. In one embodiment, a processor may include a cache including a number of cache banks. The processor may further include a number of processor cores configured to access the cache...	03/23/2010

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Class 711/5 - For multiple memory modules (e.g., banks, interleaved memory)