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| Number | Title | Issue Date |
| 8190807 | Mapping a computer program to an asymmetric multiprocessing apparatus A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a plurality of memories 12, 14. An at least partial architect... | 05/29/2012 |
| 8171200 | Serially indexing a cache memory A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table w... | 05/01/2012 |
| 8122178 | Filesystem having a filename cache A system comprising a processor, a data storage device that is accessible by the processor, and filesystem software that is executable by the processor to organize files on the data storage device are provided. The filesystem software is executable to maintain a fil... | 02/21/2012 |
| 8108587 | Free-space reduction in cached database pages A computing system stores a database comprising pages. Each of the pages is the same size. When a page is requested, a block of virtual memory addresses is associated with the page and a set of physical data storage locations is committed to the block of virtual mem... | 01/31/2012 |
| 8078790 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 12/13/2011 |
| 7984229 | Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corre... | 07/19/2011 |
| 7975093 | Cache with high access store bandwidth A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load fun... | 07/05/2011 |
| 7966442 | Cache using perfect hash function In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing d... | 06/21/2011 |
| 7877537 | Configurable cache for a microprocessor A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache l... | 01/25/2011 |
| 7870325 | Cache memory system The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-targ... | 01/11/2011 |
| 7831760 | Serially indexing a cache memory A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table w... | 11/09/2010 |
| 7783823 | Hardware device data buffer One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits... | 08/24/2010 |
| 7761648 | Caching method for NAND flash translation layer A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to... | 07/20/2010 |
| 7743200 | Instruction cache using perfect hash function In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing d... | 06/22/2010 |
| 7698495 | Computer system having logically ordered cache management A computer system is set forth that includes a processor, general memory storage, and cache memory for temporarily storing selected data requested from the general memory storage. The computer system also may include file system software that is executed by the proc... | 04/13/2010 |
| 7698496 | Cache memory observation device and method of analyzing processor A cache miss judger judges a cache miss when a cache access is executed. An entry region judger judges which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at l... | 04/13/2010 |
| 7636807 | Storage apparatus using nonvolatile memory as cache and mapping information recovering method for the storage apparatus A storage apparatus using a nonvolatile memory as a cache and a mapping information recovering method for the storage apparatus are provided. The storage apparatus includes a mapping information storage module which stores in the nonvolatile memory mapping informati... | 12/22/2009 |
| 7603510 | Semiconductor device and storage cell having multiple latch circuits A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit and receives the stored data from the first l... | 10/13/2009 |
| 7590792 | Cache memory analyzing method It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address contained in the information are totalized. The cache miss generated ... | 09/15/2009 |
| 7472218 | Assisted trace facility to improve CPU cache performance A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing ... | 12/30/2008 |
| 7451261 | Data storage device and control method with buffer control thereof Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used in its entirety or the partial continuous space should be used to rea... | 11/11/2008 |
| 7444457 | Retrieving data blocks with reduced linear addresses Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address... | 10/28/2008 |
| 7441074 | Methods and apparatus for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation Methods and apparatus are disclosed for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation. Each of the lookup units is assigned a subset of the possible values of the entries and is ... | 10/21/2008 |
| 7424587 | Methods for managing data writes and reads to a hybrid solid-state disk drive A method for writing data to a solid-state disk having a first portion of solid-state memory of a volatile nature and a second portion of solid-state memory of a non-volatile nature, and a controller for controlling data operations to the memory includes acts of (a)... | 09/09/2008 |
| 7418583 | Data dependency detection using history table of entry number hashed from memory address A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence... | 08/26/2008 |
| 7412568 | Method for thread caching Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a p... | 08/12/2008 |
| 7412569 | System and method to track changes in memory Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a trackin... | 08/12/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7406566 | Ring interconnect with multiple coherence networks A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each commu... | 07/29/2008 |
| 7404044 | System and method for data transfer between multiple processors A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency ... | 07/22/2008 |
| 7401184 | Matching memory transactions to cache line boundaries In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specif... | 07/15/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7389385 | Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system ... | 06/17/2008 |
| 7386596 | High performance storage access environment The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can prov... | 06/10/2008 |
| 7380098 | Method and system for caching attribute data for matching attributes with physical addresses A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical addr... | 05/27/2008 |
| 7380047 | Apparatus and method for filtering unused sub-blocks in cache memories A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered po... | 05/27/2008 |
| 7373466 | Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In anot... | 05/13/2008 |
| 7370150 | System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached... | 05/06/2008 |
| 7366819 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 04/29/2008 |
| 7366820 | Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A r... | 04/29/2008 |
