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| Number | Title | Issue Date |
| 8127110 | Method, system, and medium for providing interprocessor data communication A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage device; determining an area of virtual address space corresponding to data... | 02/28/2012 |
| 8108651 | Programmable signal processing circuit and method of interleaving A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for us... | 01/31/2012 |
| 8078828 | Memory mapped register file A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T−1 bits, the source index input identifying one of a plurality of unbanked registers; receiving a processor mode input to id... | 12/13/2011 |
| 8019969 | Self prefetching L3/L4 cache mechanism Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effect... | 09/13/2011 |
| 8015389 | Memory device, memory controller and memory system An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of whi... | 09/06/2011 |
| 8006066 | Method and circuit configuration for transmitting data between a processor and a hardware arithmetic-logic unit A method for transmitting data of a plurality of data types between a digital processor and a hardware arithmetic-logic unit with at least one associated table memory, first involves preselecting a base address in the table memory that (base address) is dependent on... | 08/23/2011 |
| 7996651 | Enhanced microprocessor or microcontroller An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are a... | 08/09/2011 |
| 7975125 | Method for read-only memory devices A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each add... | 07/05/2011 |
| 7966474 | System, method and computer program product for translating storage elements A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement regist... | 06/21/2011 |
| 7949852 | Memory system, computer system and memory The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then,... | 05/24/2011 |
| 7913061 | Non-volatile memory and method with memory planes alignment A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical unit... | 03/22/2011 |
| 7908458 | Ethernet controller A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one regi... | 03/15/2011 |
| 7882331 | Method and system for simultaneously supporting different block sizes on a single hard drive A method and system where a hardware platform such as a disk drive is formatted to the largest block length it is desired to read from or write to. Using commands, data can be accessed from the drive in any block length that is equal to or less than the formatted bl... | 02/01/2011 |
| 7882332 | Memory mapped register file A register system for a data processing system includes an address encoder that generates an encoded address based on a processor mode identifier and a register identifier and memory comprising 2T−1 unbanked registers. The encoded address identifies one... | 02/01/2011 |
| 7873810 | Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, ... | 01/18/2011 |
| 7861059 | Method for testing and programming memory devices and system for same A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successivel... | 12/28/2010 |
| 7814294 | Memory device, memory controller and memory system An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of whi... | 10/12/2010 |
| 7809924 | System for generating effective address Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first... | 10/05/2010 |
| 7805589 | Relative address generation Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the... | 09/28/2010 |
| 7793071 | Method and system for reducing cache conflicts Disclosed is a system and method for storing a plurality of data packets in a plurality of memory buffers in a cache memory for reducing cache conflicts. The method includes determining size of each of a plurality of data packets; storing a first data packet of the ... | 09/07/2010 |
| 7779227 | Memory management apparatus and method for optical storage system A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD) data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address fro... | 08/17/2010 |
| 7725677 | Method and apparatus for improving segmented memory addressing A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. ... | 05/25/2010 |
| 7711924 | Managing volumes in volume groups Provided are a method, system, and program for managing volumes in volume groups configured in a storage system. A first set of volumes is assigned to a first volume group and a first host is assigned to the first volume group. A second set of volumes is assigned to... | 05/04/2010 |
| 7707385 | Methods and apparatus for address translation from an external device to a memory of a processor Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of ... | 04/27/2010 |
| 7702883 | Variable-width memory A variable-width memory may comprise multiple memory banks from which data may be selectively read in such a way that overall memory access requirements may be reduced, which may result in associated reduction in power consumption. ... | 04/20/2010 |
| 7702882 | Apparatus and method for performing high-speed lookups in a routing table A lookup circuit for translating received addresses into destination addresses. The lookup circuit comprises M pipelined memory circuits for storing a trie table for translating a first received address into a first destination address. The M memory circuits are pip... | 04/20/2010 |
| 7669034 | System and method for memory array access with fast address decoder A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using... | 02/23/2010 |
| 7634636 | Device, system and method of reduced-power memory address generation Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first numbe... | 12/15/2009 |
| 7634635 | Systems and methods for reordering processor instructions Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension, wherein the instruction extension is transparent to the programming m... | 12/15/2009 |
| 7577819 | Vector indexed memory unit and method Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Indiv... | 08/18/2009 |
| 7568083 | Memory mapped register file and method for accessing the same A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by an encoded address, wherein the encoded address corresponds to at le... | 07/28/2009 |
| 7558942 | Memory mapped register file and method for accessing the same A data processing system comprises a processor to process instructions. A plurality of pipeline stages to execute instructions including a register file. The register file includes a memory unit having a plurality of memory locations, each memory location being addr... | 07/07/2009 |
| 7549038 | Method and system for determining memory chunk location using chunk header information A computer system memory is structured as contiguous memory chunks, each chunk having a header. A chunk header includes a first offset value, a sign bit associated with the first offset value, and a number of bits having values that are added to a second offset valu... | 06/16/2009 |
| 7472255 | Method for addressing a symbol in a memory and device for processing symbols A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of... | 12/30/2008 |
| 7472254 | Systems and methods for modifying a set of data objects A system and method for generating and updating a file system on a client computer. An original file system may be compared to an updated file system and the differences between the two file systems may be defined in specific data blocks. The differences may include... | 12/30/2008 |
| 7447871 | Data access program instruction encoding A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form ut... | 11/04/2008 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7437532 | Memory mapped register file A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a res... | 10/14/2008 |
| 7418573 | Address generation apparatus and operation apparatus An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count val... | 08/26/2008 |
| 7412569 | System and method to track changes in memory Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a trackin... | 08/12/2008 |
