Bizarre Patents
Smoking Cessation Lighter and Method
A lighter for tobacco products suppresses the urge to smoke by operant conditioning.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8171258 | Address generation unit with pseudo sum to accelerate load/store operations In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected valu... | 05/01/2012 |
| 8166278 | Hashing and serial decoding techniques A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that... | 04/24/2012 |
| 8028149 | Method of reading the memory plane of a contactless tag A method of reading a group of memory words from an integrated circuit memory of a contactless tag, comprising the sending by a remote interrogation unit to the contactless tag of a specific command for reading the group of memory words from a given start address, t... | 09/27/2011 |
| 7853773 | Program memory space expansion for particular processor instructions A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an exp... | 12/14/2010 |
| 7818538 | Hashing and serial decoding techniques A serial decoding technique may employ one or more circular shift register strings in which an input to an element of a shift register string may be gated by either an address input or the inverse of the address input. An output word line of the decoder may be drive... | 10/19/2010 |
| 7636834 | Method and apparatus for resetting a gray code counter Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication ... | 12/22/2009 |
| 7631164 | Modulo arithmetic A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address... | 12/08/2009 |
| 7509478 | Program memory space expansion for particular processor instructions A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an exp... | 03/24/2009 |
| 7506133 | Method and apparatus for high speed addressing of a memory space from a relatively small address space A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2M address memory space, where M is greater than N. The method and apparatus provide for (a) pr... | 03/17/2009 |
| 7475221 | Circular buffer addressing Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify... | 01/06/2009 |
| 7457937 | Method and system for implementing low overhead memory access in transpose operations Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of paral... | 11/25/2008 |
| 7421563 | Hashing and serial decoding techniques A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that... | 09/02/2008 |
| 7421564 | Incrementing successive write operations to a plurality of memory devices A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a re... | 09/02/2008 |
| 7409527 | Bidirectional data storing method A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction t... | 08/05/2008 |
| 7404061 | Permanent pool memory management method and system A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing process. The memory segment includes a plurality of memory objects, each of ... | 07/22/2008 |
| 7401202 | Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ... | 07/15/2008 |
| 7369135 | Memory management system having a forward progress bit A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a graphics system composed of multiple clients. Pages that are required ... | 05/06/2008 |
| 7366842 | Creating permanent storage on the fly within existing buffers A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache wi... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7366872 | Method for addressing configuration registers by scanning for a structure in configuration space and adding a known offset A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure ... | 04/29/2008 |
| 7366882 | Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle. ... | 04/29/2008 |
| 7363475 | Managing registers in a processor to emulate a portion of a stack The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managi... | 04/22/2008 |
| 7360040 | Interleaver for iterative decoder Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implem... | 04/15/2008 |
| 7360039 | Arrangements storing different versions of a set of data in separate memory areas and method for updating a set of data in a memory Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for un... | 04/15/2008 |
| 7342814 | Content addressable memory with reduced search current and power The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the ... | 03/11/2008 |
| 7333107 | Volume rendering apparatus and process A computer automated process is presented for accelerating the rendering of sparse volume data on Graphics Processing Units (GPUs). GPUs are typically SIMD processors, and thus well suited to processing continuous data and not sparse data. The invention allows GPUs ... | 02/19/2008 |
| 7333097 | Display apparatus and method capable of rotating an image A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address “as is” or translates th... | 02/19/2008 |
| 7330917 | Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the exponential decimation approach by a probabilistic amount. Recursive decimati... | 02/12/2008 |
| 7320038 | Method and apparatus for interfacing a LAN to a drive An interface card connects a LAN with a drive. The interface card comprises a dual port memory interface, which interfaces to the main control card of the drive. An interrupt line informs a communication processor on the main control card to update feedbacks in the ... | 01/15/2008 |
| 7319540 | Systems and methods for remote viewing of patient images A digital camera containing patient images is connected to an uploader computer and the patient's name or history is entered into the uploader computer. The uploader computer then connects to the Internet, connects to the secure host server, uploads the images to th... | 01/15/2008 |
| 7313644 | Memory device interface An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to d... | 12/25/2007 |
| 7296124 | Memory interface supporting multi-stream operation A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data occurs within sequential transactions. Each transaction is associated wit... | 11/13/2007 |
| 7293253 | Transparent interface migration using a computer-readable mapping between a first interface and a second interface to auto-generate an interface wrapper For a software application that uses a first interface, a method is provided to allow the migration of the software application to a second interface instead of the first interface. The software application may, in some situations, be migrated without having to modi... | 11/06/2007 |
| 7290118 | Address control system for a memory storage device A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The m... | 10/30/2007 |
| 7290084 | Fast collision detection for a hashed content addressable memory (CAM) using a random access memory A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, prov... | 10/30/2007 |
| 7290117 | Memory having increased data-transfer speed and related systems and methods A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes... | 10/30/2007 |
| 7286976 | Emulation of circuits with in-circuit memory Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource i... | 10/23/2007 |
| 7287115 | Multi-chip package type memory system A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, an... | 10/23/2007 |
| 7287090 | Method and system for identifying a computing device in response to a request packet According to a first embodiment, a first computing device receives a request packet originating from a client. In response to at least the request packet and a state of at least one of the first computing device and a second computing device, the first computing dev... | 10/23/2007 |
| 7269710 | Program memory space expansion for particular processor instructions A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an exp... | 09/11/2007 |
