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| Number | Title | Issue Date |
| 7549037 | Efficient off-host backup of a file set clone A method, system, computer system, and computer-readable medium that enable a secondary host that is not the file system host to create a backup of a clone file set that shares at least one data block on a storage device with an active file set. Start and end locati... | 06/16/2009 |
| 7421563 | Hashing and serial decoding techniques A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that... | 09/02/2008 |
| 7409527 | Bidirectional data storing method A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction t... | 08/05/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7395407 | Mechanisms and methods for using data access patterns The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a mem... | 07/01/2008 |
| 7386675 | Systems and methods for using excitement values to predict future access to resources Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to the resource being accessed. The system also maintains a threshold. As ... | 06/10/2008 |
| 7370138 | Mobile communication terminal including NAND flash memory and method for booting the same A mobile communication terminal with a NAND flash memory is described. The terminal includes a memory for storing address information indicative of a start address of a specific area including boot data to be read from the NAND flash memory; and a sub-controller for... | 05/06/2008 |
| 7360040 | Interleaver for iterative decoder Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implem... | 04/15/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7343470 | Techniques for sequentially transferring data from a memory device through a parallel interface Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for t... | 03/11/2008 |
| 7340562 | Cache for instruction set architecture A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number... | 03/04/2008 |
| 7325176 | System and method for accelerated information handling system memory testing Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instanc... | 01/29/2008 |
| 7293155 | Management of access to data from memory Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of d... | 11/06/2007 |
| 7290119 | Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator mo... | 10/30/2007 |
| 7290117 | Memory having increased data-transfer speed and related systems and methods A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes... | 10/30/2007 |
| 7272696 | Dynamic volume management A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a first end and second end, with a respective list of data objects associated with each end. The volume can ... | 09/18/2007 |
| 7266671 | Register addressing There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said ... | 09/04/2007 |
| 7266629 | Data transfer control device and electronic instrument generating interface signal of signal type according to interface information set in internal register A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface si... | 09/04/2007 |
| 7257651 | Sequential data transfer detection using addresses of data transfer requests to control the efficiency of processing the data transfer requests A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data transfer request may be indicated as combinable with subsequent data transf... | 08/14/2007 |
| 7254692 | Testing for operating life of a memory device with address cycling using a gray code sequence In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of l... | 08/07/2007 |
| 7254696 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit th... | 08/07/2007 |
| 7243041 | GUID, PnPID, isochronous bandwidth based mechanism for achieving memory controller thermal throttling A device to control memory bandwidth including a processing unit and a memory connected to the processing unit, the memory having a memory controller driver to issue at least one command based on a memory bandwidth requirement of another driver process. A memory con... | 07/10/2007 |
| 7243209 | Apparatus and method for speeding up access time of a large register file with wrap capability An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, addit... | 07/10/2007 |
| 7240114 | Namespace management in a distributed file system Method and system for performing a namespace operation in a distributed file system. The file system is disposed on a plurality of partition servers, and each partition server controls access to a subset of hierarchically-related, shared storage objects. Each namesp... | 07/03/2007 |
| 7225219 | Distributed caching architecture for computer networks A distributed caching technique for use in computer networks is disclosed. The illustrative embodiment is particularly advantageous in computer networks that comprises a hierarchical topology because it removes some of the computational tasks associated with caching... | 05/29/2007 |
| 7213126 | Method and processor including logic for storing traces within a trace cache A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be ass... | 05/01/2007 |
| 7210020 | Continuous interleave burst access A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read opera... | 04/24/2007 |
| 7206918 | Address predicting apparatus and methods Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for eac... | 04/17/2007 |
| 7203780 | System and method for facilitating communication between devices on a bus using tags Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with... | 04/10/2007 |
| 7197622 | Efficient mapping of signal elements to a limited range of identifiers Signal elements are mapped to a limited range of identifiers by emulating a “virtual” space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of ... | 03/27/2007 |
| 7191430 | Providing instruction execution hints to a processor using break instructions A computer system with mechanisms for providing hint instructions to a processor without altering object code instruction sequences. A computer system according to the present teachings includes elements for generating a hint instruction in response to a set of obje... | 03/13/2007 |
| 7188231 | Multimedia address generator Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when c... | 03/06/2007 |
| 7185154 | Single segment data object management A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record ... | 02/27/2007 |
| 7173853 | Nonvolatile semiconductor memory Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data... | 02/06/2007 |
| 7174442 | Data addressing A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address v... | 02/06/2007 |
| 7174432 | Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple proces... | 02/06/2007 |
| 7171469 | Apparatus and method for storing data in a proxy cache in a network In one embodiment, the invention provides an apparatus for caching data in a network, with the apparatus including a proxy cache configured to receive request for an object from a client and to fetch data blocks from a server. The proxy cache may be configured to ca... | 01/30/2007 |
| 7162606 | Multiple segment data object management A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index table objects containing defining information about the data objects in which the data are stored, such as t... | 01/09/2007 |
| 7162563 | Semiconductor integrated circuit having changeable bus width of external data signal A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal add... | 01/09/2007 |
| 7159084 | Memory controller A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller pre-calculates the number of data bursts required to retrieve all the ... | 01/02/2007 |
