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| Number | Title | Issue Date |
| 8145877 | Address generation for quadratic permutation polynomial interleaving For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address f... | 03/27/2012 |
| 8140824 | Secure code authentication A computer program product comprises a computer useable medium having a computer readable program for authentication of code, such as boot code. A memory addressing engine is employable to select a portion of a memory, as a function of a step value, as a first input... | 03/20/2012 |
| 8074050 | Electronic device and address space expansion method An address space expansion method implemented by the electronic device which includes a storage unit, wherein the storage unit includes a first storage unit and a second storage unit, comprising: responding to the user operation to generate a target address; determi... | 12/06/2011 |
| 8051272 | Method and system for generating addresses for a processor A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of instructions, and each instruction comprises at least one line. The method incl... | 11/01/2011 |
| 8028148 | Safe and efficient allocation of memory Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable image. Moreover, performance improvements are implemented over traditiona... | 09/27/2011 |
| 7953955 | Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instructio... | 05/31/2011 |
| 7934074 | Flash module with plane-interleaved sequential writes to restricted-write flash chips A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB an... | 04/26/2011 |
| 7865692 | Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instructio... | 01/04/2011 |
| 7822944 | Data format for efficient encoding and access of multiple data items in RFID tags Systems and methods for optimizing random access retrieval of a requested data item in a radio frequency identification (RFID) tag are provided. During random access retrieval, a first read of a memory bank in the RFID tag is performed. The first read providers a se... | 10/26/2010 |
| 7707384 | System and method for re-ordering memory references for access to memory A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses correspondin... | 04/27/2010 |
| 7702881 | Method and system for data transfers across different address spaces A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configure... | 04/20/2010 |
| 7634634 | Data search apparatus and a method thereof A data search apparatus and method are disclosed for searching for a target address of a target data in a memory. The data search apparatus includes a data sort module, an address assignment module, an address transformation module, and at least one comparative modu... | 12/15/2009 |
| 7634633 | Method and apparatus for memory address generation using dynamic stream descriptors Memory addresses for a data stream are generated by a stream parameter generator that calculates a set of stream parameters for each of a number of memory access patterns and a regional address generator that calculates a sequence of addresses of a memory access pat... | 12/15/2009 |
| 7587576 | Parameter storing method, parameter storage device, multi-body problem processing apparatus, and address generator circuit The object of the present invention is the reduction of memory capacity in a multi-body problem processing apparatus. In a parameter storing method in multi-body problem processing for performing a molecular dynamics calculation for a plurality of particles existing... | 09/08/2009 |
| 7558941 | Automatic detection of micro-tile enabled memory In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the me... | 07/07/2009 |
| 7555629 | Memory card providing hardware acceleration for read operations A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory ... | 06/30/2009 |
| 7502909 | Memory address generation with non-harmonic indexing A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP... | 03/10/2009 |
| 7464250 | Method to reduce disk access time during predictable loading sequences The invention discloses a method for loading data from a disk. The method may comprise comparing a current sequence of disk requests to data indicative of a previous disk request sequence. Responsive to detecting a match between the current disk sequence and the pre... | 12/09/2008 |
| 7457936 | Memory access instruction vectorization A compilation method includes converting memory access instructions that read or write less than a minimum data access unit (MDAU) to memory access instructions that read or write a multiple of the minimum data access unit, converting the memory access instructions ... | 11/25/2008 |
| 7437531 | Testing memories Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo r... | 10/14/2008 |
| 7434216 | Update package generator that employs genetic evolution to determine bank order Disclosed herein is an update package generator which may employ a bank order determination module to determine an optimum bank order of memory banks of a binary image of at least one of firmware and software. The bank order may subsequently be employed in generatio... | 10/07/2008 |
| 7421540 | Method, apparatus, and program to efficiently calculate cache prefetching patterns for loops A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, da... | 09/02/2008 |
| 7421563 | Hashing and serial decoding techniques A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that... | 09/02/2008 |
| 7418573 | Address generation apparatus and operation apparatus An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count val... | 08/26/2008 |
| 7415584 | Interleaving input sequences to memory An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency. ... | 08/19/2008 |
| 7409472 | Device controller and input/output system An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential input/output requests of the host are separated through a distribution process... | 08/05/2008 |
| 7409527 | Bidirectional data storing method A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction t... | 08/05/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7404055 | Memory transfer with early access to critical portion In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a sec... | 07/22/2008 |
| 7400591 | Method of creating an address and a discontiguous mask for a network security policy area A method of creating a discontiguous address plan for an enterprise is provided which includes determining a hierarchy of routing optimization for an enterprise, determining a number of route advertisement aggregation points at each level of the hierarchy, determini... | 07/15/2008 |
| 7395406 | System and method of large page handling in a virtual memory system A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU rec... | 07/01/2008 |
| 7395407 | Mechanisms and methods for using data access patterns The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a mem... | 07/01/2008 |
| 7394494 | Sub-sampling apparatus and method and image sensor employing the same The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The ... | 07/01/2008 |
| 7386675 | Systems and methods for using excitement values to predict future access to resources Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to the resource being accessed. The system also maintains a threshold. As ... | 06/10/2008 |
| 7383416 | Method for setting a second rank address from a first rank address in a memory module A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first r... | 06/03/2008 |
| 7380099 | Apparatus and method for an address generation circuit A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components.... | 05/27/2008 |
| 7380084 | Dynamic detection of block boundaries on memory reads In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the ce... | 05/27/2008 |
| 7373480 | Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a secon... | 05/13/2008 |
| 7370174 | Method, system, and program for addressing pages of memory by an I/O device Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual add... | 05/06/2008 |
| 7370173 | Method and system for presenting contiguous element addresses for a partitioned media library According to one embodiment of the present invention, a controller that partitions a media library for multiple host applications can, for each partition, assign a base element address for an element type and associate physical element addresses for elements of an e... | 05/06/2008 |
