Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8037282 | Register having security function and computer system including the same A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address ... | 10/11/2011 |
| 7617382 | Method and apparatus for decompressing relative addresses A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address a... | 11/10/2009 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7356708 | Decryption semiconductor circuit A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to dec... | 04/08/2008 |
| 7343471 | Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, eac... | 03/11/2008 |
| 7310800 | Method and system for patching ROM code A method and system for overriding selected ROM code functions or adding new ROM code functions within a processing system. A system designer determines an existing ROM address for the selected existing code function or a desired ROM address for the new code functio... | 12/18/2007 |
| 7290081 | Apparatus and method for implementing a ROM patch using a lockable cache A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacin... | 10/30/2007 |
| 7146457 | Content addressable memory selectively addressable in a physical address mode and a virtual address mode Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a plurality of CAM fields. At least one input selector controls access... | 12/05/2006 |
| 7143265 | Computer program product memory access system A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively wi... | 11/28/2006 |
| 7135897 | Clock resynchronizer A clock resynchronizer includes a write circuit and a read circuit. The write circuit stores input data in accordance with a first clock associated with the input data. The read circuit outputs data to be output out of the data stored in the write circuit, in accord... | 11/14/2006 |
| 7114055 | Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction... | 09/26/2006 |
| 7103749 | System and method for managing memory A new memory tuple is described that creates both a handle as well as a reference to an item within the handle. The reference is created using an offset value that defines the physical offset of the data within the memory block. Thereafter, if references are passed ... | 09/05/2006 |
| 7103705 | Computing system, and method for enabling a digital signal processor to access parameter tables through a central processing unit A computing system includes a digital signal processor, a storage medium for storing parameter tables, a central processing unit coupled to the digital signal processor and the storage medium, and a shared memory coupled to the digital signal processor and the centr... | 09/05/2006 |
| 7069415 | System and method to automatically stack and unstack Java local variables A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache coupled to the processing core, and a programmable register containing a pointer to a currently active method's... | 06/27/2006 |
| 7051138 | Interrupt-processing system for shortening interrupt latency in microprocessor The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both store an interrupt vector table individually for recording the entry ins... | 05/23/2006 |
| 7039789 | Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an array including a number of elements each including an address. The first element of the array includes ... | 05/02/2006 |
| 7010665 | Method and apparatus for decompressing relative addresses A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address a... | 03/07/2006 |
| 6986014 | System and method for using a vendor-long descriptor in ACPI for the chipset registers A system and method for using memory mapped I/O (MMIO) to manage system devices is provided. A parent device in the ACPI namespace uses (MMIO) to identify the memory addresses of its children devices. An existing, but unused, construct of ACPI is used to pass the MM... | 01/10/2006 |
| 6957322 | Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to select entries of the microcode memory. A microcode entry point genera... | 10/18/2005 |
| 6934828 | Decoupling floating point linear address A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored. ... | 08/23/2005 |
| 6928027 | Virtual dual-port synchronous RAM architecture Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional architecture used with a single-port RAM. Disclosed is a read/write memory de... | 08/09/2005 |
| 6918068 | Fault-tolerant communications system and associated methods A communications system may include a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the at least one bus device. The ... | 07/12/2005 |
| 6851037 | Method of utilization of a data storage array, and array controller therefor A number of virtual areas with virtual addresses of storage locations within the virtual areas are allocated to a data storage array, having a total physical storage capacity. Physical addresses are allocated by an array controller for the disc storage array to the ... | 02/01/2005 |
| 6816959 | Memory access system A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively wi... | 11/09/2004 |
| 6816889 | Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port memory. The dual port memory includes first and second memory ports, memor... | 11/09/2004 |
| 6792520 | System and method for using a using vendor-long descriptor in ACPI for the chipset registers A system and method for using memory mapped I/O (MMIO) to manage system devices is provided. A parent device in the ACPI namespace uses (MMIO) to identify the memory addresses of its children devices. An existing, but unused, construct of ACPI is used to pass the MM... | 09/14/2004 |
| 6775756 | Method and apparatus for out of order memory processing within an in order processor A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. ... | 08/10/2004 |
| 6732258 | IP relative addressing A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bi... | 05/04/2004 |
| 6662292 | Memory access system A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined resp... | 12/09/2003 |
| 6658553 | Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, an... | 12/02/2003 |
| 6654868 | Information storage and retrieval system Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has require... | 11/25/2003 |
| 6618803 | System and method for finding and validating the most recent advance load for a given checkload The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction conflicts with a store instruction thereby requiring a recov... | 09/09/2003 |
| 6584557 | Processor and method for generating a pointer A processor is provided for calculating an output pointer to a first data item by combination of an input pointer to a second data item with an offset. The processor includes logic for generating, in a single operation, a zero value for the output pointer... | 06/24/2003 |
| 6567908 | Method of and apparatus for processing information, and providing medium An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has... | 05/20/2003 |
| 6519692 | Method for updating a pointer to access a memory address in a DSP A processor coupled to a memory for providing a pointer in order to access a corresponding memory address, the pointer being updated by adding a predetermined increment according to logic integral with the processor. A method is disclosed for updating the... | 02/11/2003 |
| 6470439 | FIFO memory control circuit The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention relates to a FIFO memory control circuit capable of performing... | 10/22/2002 |
| 6438680 | Microprocessor When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each... | 08/20/2002 |
| 6415375 | Information storage and retrieval system Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has require... | 07/02/2002 |
| 6345336 | Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption An instruction cache memory (12) includes a clock gate circuit (26) for controlling the supply of a clock signal (CLK) to tag RAM (22). The clock gate circuit (22) supplies the clock signal (CLK) to tag RAM 22 only when there is a movement in cache line f... | 02/05/2002 |
| 6311258 | Data buffer apparatus and method for storing graphical data using data encoders and decoders A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending upon a mode of operation. The apparatus includes an encod... | 10/30/2001 |
