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| Number | Title | Issue Date |
| 8060724 | Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a first register, wherein each register of the plurality of registers ... | 11/15/2011 |
| 7827383 | Efficient on-chip accelerator interfaces to reduce software overhead In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is confi... | 11/02/2010 |
| 7444494 | Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predi... | 10/28/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7401202 | Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ... | 07/15/2008 |
| 7398370 | Information processing apparatus and method In an information processing apparatus, a program processing unit executes a program described as an object-oriented language executed by a platform-independent machine language. A monitor unit monitors a change of a network address of the information processing app... | 07/08/2008 |
| 7386702 | Systems and methods for accessing thread private data Systems and methods are provided for accessing thread private data in a computer. In one embodiment, a method is provided for accessing thread private data in a computer for a program executed by using a plurality of threads, wherein each of the plurality of threads... | 06/10/2008 |
| 7366882 | Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle. ... | 04/29/2008 |
| 7360058 | System and method for generating effective address Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first... | 04/15/2008 |
| 7356811 | Method and apparatus for referencing a constant pool in a java virtual machine A method, apparatus, and computer instructions for referencing a constant pool. A determination is made as to whether a bytecode references the constant pool. A relative offset to the constant pool is identified for the bytecode, in response to the bytecode referenc... | 04/08/2008 |
| 7308556 | Device and method for writing data in a processor to memory at unaligned location A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the... | 12/11/2007 |
| 7308555 | Processor-based structure and method for loading unaligned data A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device incl... | 12/11/2007 |
| 7308554 | Processor-based automatic alignment device and method for data movement A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device incl... | 12/11/2007 |
| 7308553 | Processor device capable of cross-boundary alignment of plural register data and the method thereof A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with plural N-bit registers, a shifter to combine a first and a second out... | 12/11/2007 |
| 7302524 | Adaptive thread ID cache mechanism for autonomic performance tuning An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected accord... | 11/27/2007 |
| 7293155 | Management of access to data from memory Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of d... | 11/06/2007 |
| 7284100 | Invalidating storage, clearing buffer entries, and an instruction therefor Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additi... | 10/16/2007 |
| 7284072 | DMA engine for fetching words in reverse order Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches... | 10/16/2007 |
| 7269711 | Methods and apparatus for address generation in processors Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the... | 09/11/2007 |
| 7254595 | Method and apparatus for storage and retrieval of very large databases using a direct pipe A method and apparatus for directly connecting very large data streams from an archive command into a backup data system using an “intelligent process.” An output stream is piped into an intelligent pipe-reading process and distributed over a set of temporary da... | 08/07/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7234025 | Microprocessor with repeat prefetch instruction A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preced... | 06/19/2007 |
| 7228325 | Bypassable adder An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the ... | 06/05/2007 |
| 7213127 | System for producing addresses for a digital signal processor A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of opera... | 05/01/2007 |
| 7206924 | Microcontroller instruction set A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is... | 04/17/2007 |
| 7203818 | Microcontroller instruction set A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is... | 04/10/2007 |
| 7203799 | Invalidation of instruction cache line during reset handling Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cac... | 04/10/2007 |
| 7197601 | Method, system and program product for invalidating a range of selected storage translation table entries Selected units of storage, such as segments of storage or regions of storage, may be invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Add... | 03/27/2007 |
| 7194602 | Data processor A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a regis... | 03/20/2007 |
| 7191318 | Native copy instruction for file-access processor with copy-rule-based validation A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and executi... | 03/13/2007 |
| 7162743 | System and method of limiting access to protected hardware addresses and processor instructions A system and method for protecting a defined range of hardware addresses or a defined set of processor instructions from being accessed or executed by unauthorized software modules. Abstraction layer code is given a range of software addresses that are permitted to ... | 01/09/2007 |
| 7152147 | Storage control system and storage control method A computer system comprises a primary volume 22P having a plurality of storage blocks P, and a differential volume 22D having a plurality of storage blocks D. Differential data corresponding to one among the plurality of storage blocks P is stored in a... | 12/19/2006 |
| 7136987 | Memory configuration apparatus, systems, and methods An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, appa... | 11/14/2006 |
| 7136990 | Fast POP operation from RAM cache using cache row value stack A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data stored into the cache. When a pop instruction is encountered, the apparat... | 11/14/2006 |
| 7133996 | Memory device and internal control method therefor A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape ... | 11/07/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7107387 | Control module comprising a ROM with reduced electrical consumption A control module (1) having the following elements: a read-only memory (ROM 2), a temporary buffer (6), into which the data of said ROM (2) can be transferred in order to be accessible from outside the control module, a read controller ( | 09/12/2006 |
| 7093085 | Device and method for minimizing puncturing-caused output delay Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from th... | 08/15/2006 |
| 7080056 | Automatic programming A method for generating a simple kind of computer based artificial consciousness, which means to give a in a computer running invention-pursuant program the capability to act and to know the effects of its actions and to plan further actions consciously. This is rea... | 07/18/2006 |
| 7069393 | Storage system providing file aware caching and file aware remote copy A computer system in which a host computer is connected to a storage unit, the storage unit operating in a unit of a file. A file attribute control unit and the storage unit execute the processing being linked together so that, in response to a request from a client... | 06/27/2006 |
