Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 8171257 | Determining an end of valid log in a log of write records using a next pointer and a far ahead pointer Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a... | 05/01/2012 |
| 8127108 | Apparatus, system and method for prefetching data in bus system A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers it to a first select circuit. In response to a signal from the master... | 02/28/2012 |
| 8095774 | Pre-fetching data into a memory Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to ... | 01/10/2012 |
| 8024547 | Virtual memory translation with pre-fetch prediction A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled ... | 09/20/2011 |
| 7984265 | Event address register history buffers for supporting profile-guided and dynamic optimizations A computer processor and a method of using the computer processor take advantage of information in the event address register of the computer processor by saving information from the event address register to an event address register history buffer. Thus, the event... | 07/19/2011 |
| 7966473 | Optimised storage addressing method The invention concerns a method for read-addressing a site among a plurality of storage units using a coded address derived from an instruction. The method comprises the following steps: a) predicting (104) the storage unit corresponding to the site to be add... | 06/21/2011 |
| 7900019 | Data access target predictions in a data processing system A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logi... | 03/01/2011 |
| 7831799 | Speculative address translation for processor using segmentation and optional paging An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses... | 11/09/2010 |
| 7831800 | Technique for prefetching data based on a stride pattern A processor system (100) includes a central processing unit (102) and a prefetch engine (110). The prefetch engine (110) is coupled to the central processing unit (102). The prefetch engine (110) is configured to detect, whe... | 11/09/2010 |
| 7774578 | Apparatus and method of prefetching data in response to a cache miss A device and method is illustrated to prefetch information based on a location of an instruction that resulted in a cache miss during its execution. The prefetch information to be accessed is determined based on previous and current cache miss information. For examp... | 08/10/2010 |
| 7739478 | Multiple address sequence cache pre-fetching A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cach... | 06/15/2010 |
| 7657726 | Context look ahead storage structures A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second m... | 02/02/2010 |
| 7644253 | Memory hub with internal cache and/or memory access prediction A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to ... | 01/05/2010 |
| 7552311 | Memory device with preread data management The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a contr... | 06/23/2009 |
| 7539844 | Prefetching indirect array accesses A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having information for determining an address of an element of the array A; detecting... | 05/26/2009 |
| 7533242 | Prefetch hardware efficiency via prefetch hint instructions A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. ... | 05/12/2009 |
| 7512770 | Buffering apparatus and buffering method using ring buffer A read unit in a buffering apparatus writes data in a memory apparatus used as a ring buffer. A determination unit determines whether data is consecutively written in the memory apparatus. When it in determined that data in consecutively written, the determination u... | 03/31/2009 |
| 7444494 | Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predi... | 10/28/2008 |
| 7444471 | Method and system for using external storage to amortize CPU cycle utilization A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in g... | 10/28/2008 |
| 7434004 | Prefetch prediction Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execut... | 10/07/2008 |
| 7430650 | Generating a set of pre-fetch address candidates based on popular sets of address and data offset counters Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to previously requested addresses and returned data to compute a set of increm... | 09/30/2008 |
| 7428627 | Method and apparatus for predicting values in a processor having a plurality of prediction modes A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP tabl... | 09/23/2008 |
| 7424578 | Computer system, compiler apparatus, and operating system A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates thr... | 09/09/2008 |
| 7421694 | Systems and methods for enhancing performance of a coprocessor Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU interventi... | 09/02/2008 |
| 7418554 | Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l... | 08/26/2008 |
| 7406581 | Speculative instruction load control A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load co... | 07/29/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7395406 | System and method of large page handling in a virtual memory system A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU rec... | 07/01/2008 |
| 7389385 | Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system ... | 06/17/2008 |
| 7386701 | Prefetching hints A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination. | 06/10/2008 |
| 7386675 | Systems and methods for using excitement values to predict future access to resources Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to the resource being accessed. The system also maintains a threshold. As ... | 06/10/2008 |
| 7383417 | Prefetching apparatus, prefetching method and prefetching program product The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a pl... | 06/03/2008 |
| 7380062 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In... | 05/27/2008 |
| 7380066 | Store stream prefetching in a microprocessor In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the loa... | 05/27/2008 |
| 7373478 | Information processing apparatus and software pre-fetch control method In an information processing apparatus (10) that includes a cache memory (560) formed from at least one hierarchy, and a pre-fetch command that speculatively transfers data or a command from a main storage (30) to the cache memory, a cache contr... | 05/13/2008 |
| 7370152 | Memory controller with prefetching capability A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodimen... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366846 | Redirection of storage access requests Provided are a method, system, and article of manufacture, wherein a controller receives a request from one of a plurality of hosts. The controller determines whether a primary storage control unit coupled to the controller is operational. A response is generated by... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
