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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 7533241 | Variable size cache memory support within an integrated circuit An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6... | 05/12/2009 |
| 7502908 | Method for providing an address format compatible with different addressing formats used for addressing different sized address spaces Provided is a method, system, and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces. An address format is used in an operating system to address storage space in a s... | 03/10/2009 |
| 7404055 | Memory transfer with early access to critical portion In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a sec... | 07/22/2008 |
| 7404049 | Method and system for managing address bits during buffered program operations in a memory device A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locatio... | 07/22/2008 |
| 7401202 | Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ... | 07/15/2008 |
| 7386700 | Virtual-to-physical address translation in a flash file system A flash memory management system for a memory for accessing data from a host, the system including physical units and virtual units of the memory and a mapping mechanism of each virtual unit into one or more physical units, wherein the number of binary bits required... | 06/10/2008 |
| 7386650 | Memory test circuit with data expander A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width... | 06/10/2008 |
| 7362732 | Tracking control in a CDMA system A tracking circuit includes a plurality of phase sections each corresponding to different phases of a despreading code. Each of the phase sections includes a correlator for producing a correlation value between a reception signal and a corresponding phase of the spr... | 04/22/2008 |
| 7356811 | Method and apparatus for referencing a constant pool in a java virtual machine A method, apparatus, and computer instructions for referencing a constant pool. A determination is made as to whether a bytecode references the constant pool. A relative offset to the constant pool is identified for the bytecode, in response to the bytecode referenc... | 04/08/2008 |
| 7352621 | Method for enhanced block management A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block is remapped to a spare block, if the block is predicted as a bad bloc... | 04/01/2008 |
| 7340501 | System, method, apparatus and program for collecting and providing information A transmission device sends status information representing status of a copier to a center through a PSTN. In the center, the status information of each copier is analyzed, and suggestion information selected based on a result of the analysis is provided to a termin... | 03/04/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7337300 | Procedure for processing a virtual address for programming a DMA controller and associated system on a chip A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual a... | 02/26/2008 |
| 7334115 | Detection, recovery and prevention of bogus branches The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic... | 02/19/2008 |
| 7330381 | Method and apparatus for a continuous read command in an extended memory array The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocate... | 02/12/2008 |
| 7324401 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 01/29/2008 |
| 7290078 | Serial memory comprising means for protecting an extended memory array during a write operation The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. T... | 10/30/2007 |
| 7281078 | Bank structure storage control device and paper matter authentication device A storage control device of bank structure is provided which comprises a CPU 1 and a storage 2 connected to CPU 1. Storage 2 detects and temporarily holds one of the bank addresses 0DF00h-7DF07h of the bank memories 9 to be read ou... | 10/09/2007 |
| 7277399 | Hardware-based route cache using prefix length The present invention defines a system and method of routing packets using a hardware-based route cache with prefix length. When a router receives a packet, the router first searches for the routing information in the hardware-based route cache and if a match is fou... | 10/02/2007 |
| 7272699 | Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page size to reduced by a factor of two (half-page activation) or four (quart... | 09/18/2007 |
| 7269710 | Program memory space expansion for particular processor instructions A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an exp... | 09/11/2007 |
| 7269711 | Methods and apparatus for address generation in processors Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the... | 09/11/2007 |
| 7265689 | Data transformation apparatus and method for transforming data block The present invention provides a data transformation apparatus for transforming a first data block into a second data block. The first data block comprises a predetermined number of bits. The data transformation apparatus comprises a control bit module, a processing... | 09/04/2007 |
| 7266667 | Memory access using multiple sets of address/data lines Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using separate addresses, in one mode of operation, and accessed using a common... | 09/04/2007 |
| 7260669 | Semiconductor integrated circuits When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the re... | 08/21/2007 |
| 7257643 | Method and apparatus to improve network routing A method and apparatus to route information in a network is described. A technique is described to search for routine information that uses a first technique on at least a portion of a first value of a network address and a second technique on at least a portion of ... | 08/14/2007 |
| 7257669 | Method for addressing a memory card, a system using a memory card, and a memory card The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one para... | 08/14/2007 |
| 7254748 | Error correcting content addressable memory A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entri... | 08/07/2007 |
| 7254699 | Aligning load/store data using rotate, mask, zero/sign-extend and or operation The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, incl... | 08/07/2007 |
| 7246198 | Content addressable memory with programmable word width and programmable priority A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of th... | 07/17/2007 |
| 7240180 | Method and system for simultaneously supporting different block sizes on a single hard drive A method and system where a hardware platform such as a disk drive is formatted to the largest block length it is desired to read from or write to. Using commands, data can be accessed from the drive in any block length that is equal to or less than the formatted bl... | 07/03/2007 |
| 7216220 | Microprocessor with customer code store A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA leve... | 05/08/2007 |
| 7206917 | Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units arid each memory unit has a unique corresponding address, the corresponding address using the binary system... | 04/17/2007 |
| 7199603 | Increment/decrement, chip select and selectable write to non-volatile memory using a two signal control protocol for an integrated circuit device An integrated circuit having a device with an adjustable parameter utilizes a two signal control protocol to select the device, perform an up/down or increment/decrement of the parameter value with or without saving the parameter value in a non-volatile memory of th... | 04/03/2007 |
| 7191309 | Double shift instruction for micro engine used in multithreaded parallel processor architecture A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.... | 03/13/2007 |
| 7191318 | Native copy instruction for file-access processor with copy-rule-based validation A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and executi... | 03/13/2007 |
| 7185324 | Compiler apparatus and method for determining locations for data in memory area Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially select... | 02/27/2007 |
| 7185128 | System and method for machine specific register addressing in external devices There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus device... | 02/27/2007 |
| 7181591 | Memory address decoding method and related apparatus by bit-pattern matching An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality of memory units, and each memory unit has a unique address. The method... | 02/20/2007 |
| 7171543 | Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the p... | 01/30/2007 |
