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| Number | Title | Issue Date |
| 8185718 | Code memory capable of code provision for a plurality of physical channels The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a p... | 05/22/2012 |
| 8082417 | Method for reducing pin counts and microprocessor using the same The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the pre... | 12/20/2011 |
| 7577818 | Microprocessor program addressing arrangement having multiple independent complete address generators An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying ... | 08/18/2009 |
| 7493467 | Address scrambling to simplify memory controller's address output multiplexer A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the m... | 02/17/2009 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7436726 | Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write addres... | 10/14/2008 |
| 7414875 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structu... | 08/19/2008 |
| 7406575 | Method and system for storing data In one example, an apparatus is provided to store data in one or more data storage systems by selecting from among at least a first operating mode and a delta replication operating mode. The apparatus comprises a means for storing data pursuant to the first operatin... | 07/29/2008 |
| 7383416 | Method for setting a second rank address from a first rank address in a memory module A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first r... | 06/03/2008 |
| 7376809 | Systems and methods for multi-frame control blocks Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives pac... | 05/20/2008 |
| 7376810 | Integrated device with multiple reading and/or writing commands An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the ad... | 05/20/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7360040 | Interleaver for iterative decoder Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implem... | 04/15/2008 |
| 7360007 | System including a segmentable, shared bus A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adap... | 04/15/2008 |
| 7356668 | System and method for using address bits to form an index into secure memory A integrity control system uses the address bits to enable protection of data stored in a system memory. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. A subset of the address lines ... | 04/08/2008 |
| 7350016 | High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memor... | 03/25/2008 |
| 7333520 | Apparatus for multiplexing signals through I/O pins One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signa... | 02/19/2008 |
| 7324401 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 01/29/2008 |
| 7313610 | Method and array for determining internet protocol addresses of a terminal array The invention relates to a method and an array for determining the IP addresses of a terminal array connected to an IP network by means of a telecommunication network. A pseudo-hardware address is administratively assigned as identifier to the subscriber connection ... | 12/25/2007 |
| 7308552 | Microcontroller An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A... | 12/11/2007 |
| 7301541 | Programmable processor and method with wide operations A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present ... | 11/27/2007 |
| 7293155 | Management of access to data from memory Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of d... | 11/06/2007 |
| 7293156 | Distributed independent cache memory A system for transferring data to and from one or more slow-access-time-mass-storage nodes which store data at respective first ranges of logical block addresses (LBAs), including a plurality of interim-fast-access-time nodes which are configured to operate independ... | 11/06/2007 |
| 7287047 | Selective data replication system and method The invention relates generally to copying electronic data. More particularly, the invention provides a computerized method for identifying, in a first backup data set, a data item satisfying a selection criterion, and copying to a second backup data set at least a ... | 10/23/2007 |
| 7286436 | High-density memory module utilizing low-density memory components A memory module comprises a plurality of memory components. Each memory component has a first bit width. The plurality of memory components are configured as one or more pairs of memory components. Each pair of memory components simulates a single virtual memory com... | 10/23/2007 |
| 7287205 | Signal testing of integrated circuit chips A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second ... | 10/23/2007 |
| 7281066 | Memory access system including support for multiple bus widths A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coup... | 10/09/2007 |
| 7268591 | Decode structure with parallel rotation A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address b... | 09/11/2007 |
| 7269709 | Memory controller configurable to allow bandwidth/latency tradeoff A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coup... | 09/11/2007 |
| 7246279 | Static random access memory (SRAM) unit and method for operating the same A static random access memory (SRAM) unit is provided having a read control module, a write control module, and a bypass. The read control module is configured to communicate a read signal defined to read from a first address in the SRAM unit. The write control modu... | 07/17/2007 |
| 7246202 | Cache controller, cache control method, and computer system In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in corr... | 07/17/2007 |
| 7246207 | System and method for dynamically performing storage operations in a computer network Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage ... | 07/17/2007 |
| 7243209 | Apparatus and method for speeding up access time of a large register file with wrap capability An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, addit... | 07/10/2007 |
| 7233534 | Electronic circuit package An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having... | 06/19/2007 |
| 7231502 | Method and system for storing data Data is stored by utilizing a first operating mode and a second operating mode. In one embodiment, in the first operating mode, a continuous replication method is utilized to store data on a primary storage system and to generate a backup version of the data on a ba... | 06/12/2007 |
| 7228354 | Method for improving performance in a computer storage system by regulating resource requests from clients A method and system for optimizing the performance of a storage system by classifying each client request for resources based on operational limits of the resources and controlling when to submit the request for processing based on service class. The operational lim... | 06/05/2007 |
| 7228538 | Method, system, and program for updating firmware to a storage system comprised of multiple controllers Disclosed is a method, system, program, and data structure for updating code in a first and second controllers. The first and second controllers are capable of accessing storage regions in a storage device. The first controller receives a code update and signals the... | 06/05/2007 |
| 7212539 | Multi-service-class definition type ATM switch A multi-service-class definition type ATM switch is basically configured by an ATM buffer device containing buffers, a data input/output device and a data processing device. The data input/output device inputs data with regard to a service class including a service ... | 05/01/2007 |
| 7194519 | System and method for administering a filer having a plurality of virtual filers A system and method enables a server, such as a filer, configured with a plurality of virtual servers, such as virtual filers, to provide two types of administrators for administering the filer. A physical filer (pfiler) administrator manages or administers common p... | 03/20/2007 |
| 7191282 | Data processing apparatus and method for determining the amount of free storage space in such an apparatus A data processing apparatus, comprising data storage having a plurality of defined storage elements, memory containing usage data indicating which of the storage elements contains data, and a processor is configured to update the usage data in response to data being... | 03/13/2007 |
