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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 7797511 | Memory refresh system and method A memory device includes a memory array containing a plurality of memory addresses. An input terminal receives a requested one of the memory addresses and a memory controller is configured to refresh a first refresh address in response to a comparison of the receive... | 09/14/2010 |
| 7526628 | Optimizing cache efficiency within application software The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cach... | 04/28/2009 |
| 7523291 | System and method for testing for memory address aliasing errors Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid add... | 04/21/2009 |
| 7519792 | Memory region access management A memory region access management technique. More particularly, at least one embodiment of the invention relates to a technique to partition memory between two or more operating systems or other software running on one or more processors. ... | 04/14/2009 |
| 7426625 | Data processing system and computer program product for support of system memory addresses with holes A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning ... | 09/16/2008 |
| 7424576 | Parallel cachelets Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content store... | 09/09/2008 |
| 7409525 | Implicit locks in a shared virtual memory system A technique coordinates access to shared data on a remote device from a local device having local physical memory. The technique involves observing a page table entry (PTE) on the remote device. The PTE is stored in a page table used for managing virtual to physical... | 08/05/2008 |
| 7398361 | Combined buffer for snoop, store merging, load miss, and writeback operations In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received f... | 07/08/2008 |
| 7395405 | Method and apparatus for supporting address translation in a virtual machine environment In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM.... | 07/01/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7386643 | Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued tran... | 06/10/2008 |
| 7349348 | Method and apparatus for determining a network topology in the presence of network address translation The present invention may be used for determining a topology of a network in the presence of network address translation. From an active client behind a translating device, communications are initiated that effect the network address translation. The communications ... | 03/25/2008 |
| 7340733 | Optimizing source code for iterative execution An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer p... | 03/04/2008 |
| 7334108 | Multi-client virtual address translation system with translation units of variable-range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 02/19/2008 |
| 7330961 | Cache control method and processor system A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual addres... | 02/12/2008 |
| 7296115 | Method of and system for controlling attributes of a plurality of storage devices A method of, and a system for, controlling attributes of a group of storage devices presents to a user a set attribute choices for one or more groups of storage devices. The user interacts with the presentation of the set of attribute choices to choose attributes fo... | 11/13/2007 |
| 7281116 | Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shoo... | 10/09/2007 |
| 7269648 | Resolving multiple master node conflict in a DDB In a computer network having a plurality of computer nodes, a directory database (DDB) distributed throughout the network in each of the nodes, the contents of the DDB being maintained consistent or replicated throughout the network through the use of one of its nod... | 09/11/2007 |
| 7266728 | Circuit for monitoring information on an interconnect A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further ... | 09/04/2007 |
| 7266652 | System and method for managing data consistency between different data volumes on one or more data storage systems in a data storage environment This invention enables managing data consistency between different data volumes by managing I/O traffic in a data storage environment. A methodology for managing data consistency, in accordance with the principles of the invention, comprises the steps of arresting p... | 09/04/2007 |
| 7260745 | Detection of information on an interconnect In a system comprising an interconnect and a plurality of modules connected to said interconnect for putting information onto the interconnect, a circuit comprising circuitry for receiving at least part of said of said information; circuitry for determining if said ... | 08/21/2007 |
| 7251717 | Semiconductor memory device While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for on... | 07/31/2007 |
| 7251719 | Recording medium playback apparatus In one aspect of the invention, text data recorded on a CD conforming to the CD-TEXT format is displayed using a minimum amount of memory. Storage capacity to be used per data item is calculated by dividing the available storage capacity by the number of text data i... | 07/31/2007 |
| 7246272 | Duplicate network address detection A plurality of data packets encoded according to a first protocol are received which encapsulate data encoded according to a second protocol. A first source address is extracted from the packets according to the first protocol, it is determined whether or not the fi... | 07/17/2007 |
| 7243206 | Method and apparatus for using a RAM memory block to remap ROM access requests A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data... | 07/10/2007 |
| 7240183 | System and method for detecting instruction dependencies in multiple phases Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of instructions. Younger instructions having potential dependencies on older instr... | 07/03/2007 |
| 7240179 | System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is ina... | 07/03/2007 |
| 7234027 | Instructions for test & set with selectively enabled cache invalidate A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the... | 06/19/2007 |
| 7222221 | Maintaining coherency of derived data in a computer system A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in mem... | 05/22/2007 |
| 7219116 | Data processing apparatus A data processing apparatus includes address generation circuit, an address translation circuit, a selection circuit, a memory, a shifter, an ALU and a mixing circuit. The address generation circuit generates a logical address for data including 10 bit imaginary par... | 05/15/2007 |
| 7216201 | Parallel cachelets Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content store... | 05/08/2007 |
| 7206916 | Partial address compares stored in translation lookaside buffer A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation ... | 04/17/2007 |
| 7194597 | Method and apparatus for sharing TLB entries A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may ... | 03/20/2007 |
| 7181590 | Method for page sharing in a processor with multiple threads and pre-validated caches A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to ma... | 02/20/2007 |
| 7177980 | Cache storage system and method A cache storage system and method are provided for saving storage space in a cache, the system and method for use in a data storage system having multiple storage devices and multiple virtual addresses, each virtual address having a data object associated therewith.... | 02/13/2007 |
| 7162608 | Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial... | 01/09/2007 |
| 7133995 | Dynamic page conflict prediction for DRAM A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a value indicating the pattern of page conflicts encountered by a memory... | 11/07/2006 |
| 7130983 | System and method for reference count regeneration In a disk-based data storage system, a controller configured to control a reference count regeneration operation, the controller includes a control register, an address register, a status register, a boundary register, and an embedded memory. The control register ma... | 10/31/2006 |
| 7124276 | Optimizing cache efficiency within application software The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cach... | 10/17/2006 |
| 7120836 | System and method for increasing cache hit detection performance A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs independent of and concurrent with error detection and correction operations, ... | 10/10/2006 |
