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| Number | Title | Issue Date |
| 8151086 | Early detection of an access to de-allocated memory Disclosed is a method of detecting an access to de-allocated memory, comprising: creating a pool of fixed size memory blocks that are a non-zero integer multiple of a page size of a processor; receiving a request for an allocation of a block of memory; recording a s... | 04/03/2012 |
| 8060723 | Memory management device A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segmen... | 11/15/2011 |
| 7953953 | Method and apparatus for reducing page replacement time in system using demand paging technique A method and apparatus for reducing a page replacement time in a system using a demand paging technique are provided. The apparatus includes a memory management unit which transmits a signal indicating that a page fault occurs, a device driver which reads a page hav... | 05/31/2011 |
| 7734892 | Memory protection and address translation hardware support for virtual machines A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application on a host computer system, executing a first virtual machine application within a fir... | 06/08/2010 |
| 7716453 | Descriptor-based memory management unit and method for memory management A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; an... | 05/11/2010 |
| 7620793 | Mapping memory partitions to virtual memory pages Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page t... | 11/17/2009 |
| 7603539 | Systems and methods for multi-frame control blocks Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives pac... | 10/13/2009 |
| 7484074 | Method and system for automatically distributing real memory between virtual memory page sizes A method, system and computer program product for allocating real memory to virtual memory page sizes when all real memory is in use includes, in response to a page fault, selecting a page frame for a virtual page. In response to determining that said page does not ... | 01/27/2009 |
| 7444637 | Systems and methods for scheduling coprocessor resources in a computing system Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is provided achieving benefits over cooperative multitasking by any one or m... | 10/28/2008 |
| 7426625 | Data processing system and computer program product for support of system memory addresses with holes A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning ... | 09/16/2008 |
| 7406575 | Method and system for storing data In one example, an apparatus is provided to store data in one or more data storage systems by selecting from among at least a first operating mode and a delta replication operating mode. The apparatus comprises a means for storing data pursuant to the first operatin... | 07/29/2008 |
| 7398353 | Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A d... | 07/08/2008 |
| 7383414 | Method and apparatus for memory-mapped input/output A method of managing memory mapped input/output (I/O) for a run-time environment is disclosed, in which opaque references are used for accessing information blocks included in files used in a dynamic run-time environment. The information block is stored in a shared ... | 06/03/2008 |
| 7376809 | Systems and methods for multi-frame control blocks Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives pac... | 05/20/2008 |
| 7370123 | Information processing apparatus A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A ... | 05/06/2008 |
| 7366865 | Enqueueing entries in a packet queue referencing packets Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area refe... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363491 | Resource management in security enhanced processors A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory. ... | 04/22/2008 |
| 7363464 | Apparatus and method for reduction of processor power consumption A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Onc... | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7356664 | Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the ... | 04/08/2008 |
| 7356667 | Method and apparatus for performing address translation in a computer system An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or... | 04/08/2008 |
| 7356026 | Node translation and protection in a clustered multiprocessor system A method of node translation for communicating over virtual channels in a clustered multiprocessor system using connection descriptors (CDs), which specify the endpoint nodes for virtual connections. The system includes a local processing element node, a remote proc... | 04/08/2008 |
| 7350053 | Software accessible fast VA to PA translation A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address tra... | 03/25/2008 |
| 7343404 | Efficient representation of system network management object identifiers Systems and methods for efficient storage of network management object identifiers are provided. Object identifiers such as SNMP MIB object identifiers are stored in a compressed form. In one embodiment, a single integer represents multiple elements of an object ide... | 03/11/2008 |
| 7343441 | Method and apparatus of remote computer management A computer being controlled is coupled via a communications bus to at least one other device comprising one or more authorized management devices. The one or more authorized management devices are coupled to a management port. Only management commands received from ... | 03/11/2008 |
| 7343471 | Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, eac... | 03/11/2008 |
| 7337360 | Stored memory recovery system Various embodiments of systems and methods for preserving saved memory states to which a computer system can be restored are disclosed. In certain embodiments, the systems and methods intercept write operations to protected memory locations and redirect them to alte... | 02/26/2008 |
| 7334109 | Method and apparatus for improving segmented memory addressing A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. ... | 02/19/2008 |
| 7330936 | System and method for power efficient memory caching A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current has... | 02/12/2008 |
| 7330960 | Dynamic allocation of computer memory In one embodiment, a method is provided for storing data in a physical storage having at least one portion of unused memory, comprising maintaining a first list comprising one or more records associated with respective segments within the unused memory, and receivin... | 02/12/2008 |
| 7328430 | Method for analyzing data and performing lexical analysis A system and method provide the ability to construct lexical analyzers on the fly in an efficient and pervasive manner. The system and method split the table describing the automata into two distinct tables and splits the lexical analyzer into two phases, one for ea... | 02/05/2008 |
| 7318141 | Methods and systems to control virtual machines Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS compon... | 01/08/2008 |
| 7310721 | Shadow page tables for address translation control In a computer system that employs virtual memory, multiple versions of a given page are stored: a directory version, a table version, and a data version. The data version contains the data that a software object believes to be stored in the page. The directory and t... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7296139 | In-memory table structure for virtual address translation system with translation units of variable range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 11/13/2007 |
| 7296136 | Methods and systems for loading data from memory According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of the at least one memory device, determining a second memory location ... | 11/13/2007 |
| 7293157 | Logically partitioning different classes of TLB entries within a single caching structure One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a has... | 11/06/2007 |
| 7293121 | DMA controller utilizing flexible DMA descriptors A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second me... | 11/06/2007 |
