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| Number | Title | Issue Date |
| 8190853 | Calculator and TLB control method A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. ... | 05/29/2012 |
| 8171255 | Optimization of paging cache protection in virtual environment A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running g... | 05/01/2012 |
| 8156309 | Translation look-aside buffer with variable page sizes Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of ... | 04/10/2012 |
| 8145876 | Address translation with multiple translation look aside buffers A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. Whe... | 03/27/2012 |
| 8140823 | Multithreaded processor with lock indicator Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking... | 03/20/2012 |
| 8140822 | System and method for maintaining page tables used during a logical partition migration Maintaining data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table stores a plurality of page entries mad... | 03/20/2012 |
| 8117422 | Fast address translation for linear and circular modes The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual a... | 02/14/2012 |
| 8108650 | Translation lookaside buffer (TLB) with reserved areas for specific sources In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the req... | 01/31/2012 |
| 8095773 | Dynamic address translation with translation exception qualifier What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the v... | 01/10/2012 |
| 8082416 | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a... | 12/20/2011 |
| 8037281 | Miss-under-miss processing and cache flushing Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a syste... | 10/11/2011 |
| 8019968 | 3-dimensional L2/L3 cache array to hide translation (TLB) delays Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effect... | 09/13/2011 |
| 8010770 | Caching device for NAND flash translation layer A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash mem... | 08/30/2011 |
| 7996650 | Microprocessor that performs speculative tablewalks A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address speci... | 08/09/2011 |
| 7991977 | Advanced processor translation lookaside buffer management in a multithreaded system An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 08/02/2011 |
| 7987337 | Translation lookaside buffer prediction mechanism A memory management unit includes a translation lookaside buffer including a page table. The page table includes M entries where M is an integer greater than zero. A register interface selects one of the M entries. The translation lookaside buffer calculates an effe... | 07/26/2011 |
| 7979669 | Method and system for caching attribute data for matching attributes with physical addresses A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical addr... | 07/12/2011 |
| 7945762 | Method and apparatus for memory management in a non-volatile memory system using a block table An invention is provided for memory management in a non-volatile memory which includes a plurality of memory blocks. The invention includes loading a block table from a memory block of the non-volatile memory into system memory, where the block table includes, inter... | 05/17/2011 |
| 7941631 | Providing metadata in a translation lookaside buffer (TLB) In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associ... | 05/10/2011 |
| 7921276 | Applying quality of service (QoS) to a translation lookaside buffer (TLB) In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identif... | 04/05/2011 |
| 7917725 | Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of... | 03/29/2011 |
| 7917726 | Using an IOMMU to create memory archetypes In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory s... | 03/29/2011 |
| 7900017 | Mechanism for remapping post virtual machine memory pages According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the proce... | 03/01/2011 |
| 7840776 | Translated memory protection apparatus for an advanced microprocessor A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has b... | 11/23/2010 |
| 7822943 | Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs) Systems, methods and computer program products for improving data stream prefetching in a microprocessor are described herein. The method includes the steps of: 1) translating an address associated with a first type of memory access request in a first translation lo... | 10/26/2010 |
| 7809923 | Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU) In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translatio... | 10/05/2010 |
| 7809922 | Translation lookaside buffer snooping within memory coherent system A node of a multiple-node system includes a translation lookaside buffer (TLB), a cache, and a TLB snoop mechanism. The node shares memory with other nodes of the multiple-node systems, and is connected with the other nodes via a bus. The TLB snooping mechanism snoo... | 10/05/2010 |
| 7805588 | Caching memory attribute indicators with cached memory data field A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual... | 09/28/2010 |
| 7797509 | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a... | 09/14/2010 |
| 7797510 | Memory management for virtual address space with translation units of variable range size In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges ma... | 09/14/2010 |
| 7793070 | Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on one or more missed virtual addresses. Entries of a first translation l... | 09/07/2010 |
| 7788464 | Scalability of virtual TLBs for multi-processor virtual machines Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete bef... | 08/31/2010 |
| 7783858 | Reducing memory overhead of a page table in a dynamic logical partitioning environment Mechanisms for reducing memory overhead of a page table in a dynamic logical partitioning (LPAR) environment are provided. Each LPAR, upon its creation, is allowed to declare any maximum main memory size for the LPAR as long as the aggregate maximum main memory size... | 08/24/2010 |
| 7783859 | Processing system implementing variable page size memory organization A processing system includes memory management software responsive to changes in a page table. The memory management software consolidates contiguous page table entries into one or more page table entries that have larger memory page sizes. The memory management sof... | 08/24/2010 |
| 7689806 | Method and system to indicate an exception-triggering page within a microprocessor A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual a... | 03/30/2010 |
| 7681012 | Method, system and device for handling a memory management fault in a multiple processor device A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor acces... | 03/16/2010 |
| 7673116 | Input/output memory management unit that implements memory attributes based on translation data In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory s... | 03/02/2010 |
| 7653803 | Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU) In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translatio... | 01/26/2010 |
| 7653802 | System and method for using address lines to control memory usage A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The a... | 01/26/2010 |
| 7650482 | Enhanced shadow page table algorithms Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the operating system maintains it's own guest page tables. These page tabl... | 01/19/2010 |
