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| Number | Title | Issue Date |
| 8180996 | Distributed computing system with universal address system and method A distributed computing system that incorporates enhanced distributed storage and a universal address system and method are provided. ... | 05/15/2012 |
| 8180995 | Logical address offset in response to detecting a memory formatting operation The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting f... | 05/15/2012 |
| 8176295 | Logical-to-physical address translation for a removable data storage device A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the ... | 05/08/2012 |
| 8171254 | Memory controller and memory control method According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is ... | 05/01/2012 |
| 8156308 | Supporting multiple byte order formats in a computer system Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory... | 04/10/2012 |
| 8151085 | Method for address translation in virtual machines The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a ... | 04/03/2012 |
| 8135938 | Real time paged computing device and method of operation A component of a computing device, such as the kernel of an operating system, is arranged to identify real time processes running on the device and transparently lock the memory owned by such processes to avoid them being paged out. The kernel is also able to inspec... | 03/13/2012 |
| 8135939 | Robust index storage for non-volatile memory A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system w... | 03/13/2012 |
| 8127107 | Virtualization with merged guest page table and shadow page directory In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table and a shadow page directory used by the virtuali... | 02/28/2012 |
| 8122224 | Clearing selected storage translation buffer entries bases on table origin address An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region t... | 02/21/2012 |
| 8117420 | Buffer management structure with selective flush A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transa... | 02/14/2012 |
| 8117421 | Data structure for enforcing consistent per-physical page cacheability attributes A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor address... | 02/14/2012 |
| 8103851 | Dynamic address translation with translation table entry format control for indentifying format of the translation table entry What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual addr... | 01/24/2012 |
| 8099579 | System and method for cache-locking mechanism using segment table attributes for replacement class ID determination A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in... | 01/17/2012 |
| 8099581 | Synchronizing a translation lookaside buffer with an extended paging table A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), ... | 01/17/2012 |
| 8099580 | Translation look-aside buffer with a tag memory and method therefor A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage porti... | 01/17/2012 |
| 8086822 | In-place shadow tables for virtualization In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table used by the virtualization software wherein at l... | 12/27/2011 |
| 8078827 | Method and apparatus for caching of page translations for virtual machines A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address to a first guest-physical memor... | 12/13/2011 |
| 8074047 | System and method for content replication detection and elimination in main memory A system and method for effectively increasing the amount of data that can be stored in the main memory of a computer, particularly, by a hardware enhancement of a memory controller apparatus that detects duplicate memory contents and eliminates duplicate memory con... | 12/06/2011 |
| 8065501 | Indexing a translation lookaside buffer (TLB) A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to gen... | 11/22/2011 |
| 8060722 | Hardware assistance for shadow page table coherence with guest page mappings Some embodiments of the present invention include an execution unit of a processor and a memory management unit interposed between the execution unit and an interface to memory suitable for storage of both guest page tables maintained by a guest operating system and... | 11/15/2011 |
| 8055877 | Translated memory protection apparatus for an advanced microprocessor A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has b... | 11/08/2011 |
| 8041923 | Load page table entry address instruction execution based on an address translation format control field What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be perf... | 10/18/2011 |
| 8037280 | System and method for improving memory locality of virtual machines A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to th... | 10/11/2011 |
| 8024546 | Opportunistic page largification Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level before the last level of the hierarchical page table system adjusted to ... | 09/20/2011 |
| 8024545 | Efficient prefetching and asynchronous writing for flash memory Disclosed herein are a flash file system and an address translation method. The flash file system includes a file system, a Flash Translation Layer (FTL), and flash memory. The FTL receives Local Block Addresses (LBAs) from the file system, and translates the LBAs i... | 09/20/2011 |
| 8019967 | Robust index storage for non-volatile memory A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system w... | 09/13/2011 |
| 8015388 | Bypassing guest page table walk for shadow page table entries not present in guest page table A method and system are provided that does not perform a page walk on the guest page tables if the shadow page table entry corresponding to the guest virtual address for accessing the virtual memory indicates that a corresponding mapping from the guest virtual addre... | 09/06/2011 |
| 7996649 | Translation look-aside buffer with look-up optimized for programmable logic resource utilization A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third ... | 08/09/2011 |
| 7984263 | Structure for a memory-centric page table walker A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the m... | 07/19/2011 |
| 7984264 | Maintaining reverse mappings in a virtualized computer system For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest ph... | 07/19/2011 |
| 7966472 | Method of managing a memory including elements provided with identity information indicative of the ancestry of said elements A method of managing a memory having stored elements that are organized in a hierarchy, each having a header containing individual identity information and a body containing data, the identity information of each element being encoded on a plurality of bits each of ... | 06/21/2011 |
| 7945761 | Maintaining validity of cached address mappings A method is provided for creating and maintaining the validity of a cache group including one or more cache elements. Each of the cache elements corresponds to a different address space in a virtual memory of a computer system. Each of the cache elements include one... | 05/17/2011 |
| 7937555 | Data processing system and computer program product to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. A page is reserved in system memory. This reserved page is made unavai... | 05/03/2011 |
| 7937556 | Minimizing TLB comparison size In one embodiment, a system comprises one or more registers configured to store a plurality of values that identify a virtual address space (collectively a tag), a translation lookaside buffer (TLB), and a control unit coupled to the TLB and the one or more register... | 05/03/2011 |
| 7934073 | Method for performing jump and translation state change at the same time A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps t... | 04/26/2011 |
| 7930515 | Virtual memory management A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective... | 04/19/2011 |
| 7917723 | Address translation table synchronization A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used ... | 03/29/2011 |
| 7917724 | Protection of user-level applications based on page table information In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator ind... | 03/29/2011 |
| 7913059 | Information processing device, data transfer method, and information storage medium The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device imm... | 03/22/2011 |
