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| Number | Title | Issue Date |
| 8190851 | Resistance variable memory device A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs... | 05/29/2012 |
| 8166277 | Data prefetching using indirect addressing A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the... | 04/24/2012 |
| 8161264 | Techniques for data prefetching using indirect addressing with offset A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the... | 04/17/2012 |
| 8161265 | Techniques for multi-level indirect data prefetching A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of ... | 04/17/2012 |
| 8161263 | Techniques for indirect data prefetching A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The ... | 04/17/2012 |
| 8131974 | Access speculation predictor implemented via idle command processing resources An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative re... | 03/06/2012 |
| 8127106 | Access speculation predictor with predictions based on a domain indicator of a cache line An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special in... | 02/28/2012 |
| 8122223 | Access speculation predictor with predictions based on memory region prior requestor tag information An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester ... | 02/21/2012 |
| 8122222 | Access speculation predictor with predictions based on a scope predictor An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the ... | 02/21/2012 |
| 7669033 | Pretranslating input/output buffers in environments with multiple page sizes Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame ... | 02/23/2010 |
| 7543132 | Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a ... | 06/02/2009 |
| 7536530 | Method and apparatus for determining a dynamic random access memory page management implementation A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters ... | 05/19/2009 |
| 7509472 | Collapsible front-end translation for instruction fetch Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer... | 03/24/2009 |
| 7444494 | Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predi... | 10/28/2008 |
| 7434004 | Prefetch prediction Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execut... | 10/07/2008 |
| 7434005 | Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access inter... | 10/07/2008 |
| 7426625 | Data processing system and computer program product for support of system memory addresses with holes A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning ... | 09/16/2008 |
| 7421694 | Systems and methods for enhancing performance of a coprocessor Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU interventi... | 09/02/2008 |
| 7418572 | Pretranslating input/output buffers in environments with multiple page sizes Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame ... | 08/26/2008 |
| 7418554 | Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l... | 08/26/2008 |
| 7409472 | Device controller and input/output system An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential input/output requests of the host are separated through a distribution process... | 08/05/2008 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7398377 | Apparatus and method for target address replacement in speculative branch target address cache An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used... | 07/08/2008 |
| 7389385 | Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system ... | 06/17/2008 |
| 7386701 | Prefetching hints A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination. | 06/10/2008 |
| 7383415 | Hardware demapping of TLBs shared by multiple threads In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of stran... | 06/03/2008 |
| 7363453 | Method and apparatus for improving storage device performance by selective volume swapping based on hot spot analysis An optimizer process in a storage system automatically selects access activity data for storage devices in the system during periods of interest so that a volume-swapping optimization analysis is based on desired device performance information and thus yields improv... | 04/22/2008 |
| 7360058 | System and method for generating effective address Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first... | 04/15/2008 |
| 7346755 | Memory quality assurance An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configu... | 03/18/2008 |
| 7343525 | Method and apparatus of detecting error of access wait signal A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to... | 03/11/2008 |
| 7340584 | Sequential nibble burst ordering for data A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address infor... | 03/04/2008 |
| 7334092 | Method and apparatus for scoring data storage devices for participating in logical volume exchange process During sampling intervals, pairs of swap scores are assigned to respective pairs of storage devices of a storage system, each swap score pair indicating an amount of system performance improvement for a swap of logical volumes between source and target storage devic... | 02/19/2008 |
| 7334088 | Page descriptors for prefetching and memory management A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it... | 02/19/2008 |
| 7328312 | Method and bus prefetching mechanism for implementing enhanced buffer control A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. Th... | 02/05/2008 |
| 7328433 | Methods and apparatus for reducing memory latency in a software application Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A perfo... | 02/05/2008 |
| 7327616 | Non-volatile semiconductor memory device The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit li... | 02/05/2008 |
| 7318142 | System and method for dynamically adjusting read ahead values based upon memory usage A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the us... | 01/08/2008 |
| 7310708 | Cache system with groups of lines and with coherency for both single lines and groups of lines In a computer system with caching, memory transactions can retrieve and store groups of lines. Coherency states are maintained for groups of lines, and for individual lines. A single coherency transaction, and a single address transaction, can then result in the tra... | 12/18/2007 |
| 7305526 | Method, system, and program for transferring data directed to virtual memory addresses to a device memory Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering ... | 12/04/2007 |
| 7305669 | Software upgrades with multiple version support A method and system thereof for supporting multiple versions of software, such as software organized as components or objects. In one embodiment, a software component (e.g., a new object) is implemented on a server node. A translator is created on the server node. T... | 12/04/2007 |
