Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8190849 | Sharing physical memory locations in memory devices A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additi... | 05/29/2012 |
| 8166274 | Data writing in system with alignment restriction or vector-based systems A method for writing data in a system with alignment restriction, where first destination data generated from first source data located in a storage range starting at a first source position is written in a storage range starting at a non-aligned position. The metho... | 04/24/2012 |
| 8127104 | Alignment matrix memory copy In the various embodiments, memory controllers, methods and systems are described. A system can include a memory controller configured to, compose a characteristic key from a source address and a destination address for a memory copy; and invoke a memory copy routin... | 02/28/2012 |
| 8095769 | Method for address comparison and a device having address comparison capabilities A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of... | 01/10/2012 |
| 8078583 | Systems and methods for performing storage operations using network attached storage Systems and methods for performing hierarchical storage operations on electronic data in a computer network are provided. In one embodiment, the present invention may store electronic data from a network device to a network attached storage (NAS) device pursuant to ... | 12/13/2011 |
| 7996645 | Log-structured file system for disk drives with shingled writing Data is written to a hard disk drive using shingled writing principles, i.e., each data track is partially overwritten when an immediately contiguous data track is written. One or more contiguous data tracks establish a band, and a band establishes a respective segm... | 08/09/2011 |
| 7996646 | Efficient encoding for detecting load dependency on store with misalignment In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a... | 08/09/2011 |
| 7873808 | Method and system for synchronizing direct access storage volumes A method and system for synchronizing direct access storage volumes designated as managed by storage management software with direct access storage volumes available to a computer system. An identifier of a volume is provided. The volume is connected to and availabl... | 01/18/2011 |
| 7870361 | Aligning IP payloads on memory boundaries for improved performance at a switch A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module modifies the frame to shi... | 01/11/2011 |
| 7836273 | Fast data access through page manipulation A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to sto... | 11/16/2010 |
| 7831798 | Method to achieve partial structure alignment A computer-implemented method including receiving a set of data having a mapping. The set of data has groups of subsets of data. The mapping describes in what order the groups of subsets of data are to be stored in a memory. The mapping also describes the offsets of... | 11/09/2010 |
| 7809919 | Automatic data block misalignment detection and correction in a computer system utilizing a hard disk subsystem An embodiment of a data misalignment correction method for a mass storage controller system that couples drives having large internal block sizes to a computer operating system having input/output data block requests, including automatically determining an amount of... | 10/05/2010 |
| 7765380 | Fast data access through page manipulation A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to sto... | 07/27/2010 |
| 7721066 | Efficient encoding for detecting load dependency on store with misalignment In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a... | 05/18/2010 |
| 7702879 | Assigning alias addresses to base addresses Provided are a method, system, and article of manufacture for assigning alias addresses to base addresses. An assignment is provided of base addresses to the devices. The base addresses are used to access the devices assigned to the base addresses. An assignment is ... | 04/20/2010 |
| 7673115 | Data operation validation Described are techniques for processing a data operation. A data operation is received at a data storage system. The data operation requests a modification of data stored in the data storage system. A first address is obtained that represents a starting address of t... | 03/02/2010 |
| 7610469 | Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst tra... | 10/27/2009 |
| 7484069 | Watchpointing unaligned data accesses A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in a guard mode. In the guard mode of operation a watchpoint comparator... | 01/27/2009 |
| 7480783 | Systems for loading unaligned words and methods of operating the same Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a method of operating the system comprising: loading a first aligned word ... | 01/20/2009 |
| 7472250 | Storage control device, and control method for storage control device The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device... | 12/30/2008 |
| 7421561 | Instruction set for efficient bit stream and byte stream I/O A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. ... | 09/02/2008 |
| 7412584 | Data alignment micro-architecture systems and methods Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an in... | 08/12/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7401202 | Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ... | 07/15/2008 |
| 7395404 | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array Alignment of clusters to pages is provided in a non-volatile memory system that receives data from a host in clusters and writes data to a memory array in units of a page. Alignment is implemented within each block using offsets in logical-to-physical mapping of dat... | 07/01/2008 |
| 7386699 | Aligning IP payloads on memory boundaries for improved performance at a switch A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module prefixes non-data bits to... | 06/10/2008 |
| 7380084 | Dynamic detection of block boundaries on memory reads In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the ce... | 05/27/2008 |
| 7369657 | Cryptography accelerator application program interface Methods and apparatus are provided for making function calls to various cryptography accelerators. An application program interface abstraction layer coupled to a cryptography accelerator receives generic function calls from designer configured software and performs... | 05/06/2008 |
| 7369574 | Multi-service segmentation and reassembly device that is operable in an ingress mode or in an egress mode A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or ... | 05/06/2008 |
| 7370184 | Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post pro... | 05/06/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7366819 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 04/29/2008 |
| 7362833 | Dynamic special character selection for use in byte alignment circuitry Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and t... | 04/22/2008 |
| 7360055 | Two address map for transactions between an X-bit processor and a Y-bit wide memory Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words o... | 04/15/2008 |
| 7356664 | Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the ... | 04/08/2008 |
| 7352749 | Device for checking numbers and method for checking numbers A device for checking numbers consists of a multiplexer (101) with a controller module (106) linked to it. An output of the multiplexer is connected to a first input of a register (102), which is an element of memory, while a first output of the... | 04/01/2008 |
| 7340495 | Superior misaligned memory load and copy using merge hardware Method, apparatus, and program means for performing misaligned memory load and copy using aligned memory operations together with a SIMD merge instruction. The method of one embodiment comprises determining whether a memory operation involves a misaligned memory add... | 03/04/2008 |
| 7337272 | Method and apparatus for caching variable length instructions An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary positi... | 02/26/2008 |
| 7333966 | Systems, methods, and software for hyperlinking names Hyperlinking or associating documents to other documents based on the names of people in the documents has become more desirable. Although there is an automated system for installing such hyperlinks into judicial opinions, the system is not generally applicable to o... | 02/19/2008 |
| 7330959 | Use of MTRR and page attribute table to support multiple byte order formats in a computer system Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memo... | 02/12/2008 |
