Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 8032687 | Method, system, and apparatus for supporting limited address mode memory access Supporting limited address mode memory access involves receiving a write request from the processor targeted to a first predetermined address. A data portion of the write request includes a target address of the system memory. In response to determining the write re... | 10/04/2011 |
| 7987190 | Filesystem having a filename cache A system comprising a processor, a data storage device that is accessible by the processor, and filesystem software that is executable by the processor to organize files on the data storage device are provided. The filesystem software is executable to maintain a fil... | 07/26/2011 |
| 7917005 | Information recording device, information recording method, information recording program and recording medium A CDA processing section extracts an unused area of an information recording medium via a disc status management section and a drive control section. The CDA processing section divides the extracted unused areas by a division criteria value MAS, which allows continu... | 03/29/2011 |
| 7908276 | Filesystem having a filename cache A system comprising a processor, a data storage device that is accessible by the processor, and filesystem software that is executable by the processor to organize files on the data storage device are provided. The filesystem software is executable to maintain a fil... | 03/15/2011 |
| 7865656 | Storage controller and storage control method A storage controller that can control memory addresses even when a memory module having a different device configuration than an already mounted memory module is added as an expansion module. More specifically, a storage controller for controlling a storage unit tha... | 01/04/2011 |
| 7793033 | Serial memory comprising means for protecting an extended memory array during a write operation The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. T... | 09/07/2010 |
| 7536498 | Method and apparatus for address mapping A method and apparatus for address mapping are provided, wherein the method sets a first address region that is accessible by a processor when a system is booted and a second address region that is expanded by a virtual address, respectively. The first and second ad... | 05/19/2009 |
| 7461196 | Computer system having an expansion device for virtualizing a migration source logical unit A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration s... | 12/02/2008 |
| 7412585 | Method for controlling disk drive using an address translation table Embodiments of the invention achieve data write in an appending manner by conversion from a logical block address to a physical block address in a HDD that has only one storage device and does not have a large-scale cache memory. In one embodiment, a check is made a... | 08/12/2008 |
| 7409477 | Memory card having a processor coupled between host interface and second interface wherein internal storage code provides a generic interface between host interface and processor A memory card comprising a first modular component that comprises a first interface and first conductors and a data mover that comprises second conductors coupled to the first conductors. The first modular component is replaceable with a second modular component tha... | 08/05/2008 |
| 7404060 | Apparatus, program, and method for managing usage of memory A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size that is determined by area size information included in the area allocati... | 07/22/2008 |
| 7401178 | Expanded memory space in environments including virtual machines Accessing data comprises executing a set of computer instructions in a first environment, wherein the first environment has limited addressing capability to address memory up to a size limit, specifying a set of data in a memory space of a second environment, wherei... | 07/15/2008 |
| 7401202 | Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ... | 07/15/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7389097 | Receiver, transceiver circuit, signal transmission method, and signal transmission system A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on t... | 06/17/2008 |
| 7386650 | Memory test circuit with data expander A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width... | 06/10/2008 |
| 7386596 | High performance storage access environment The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can prov... | 06/10/2008 |
| 7383416 | Method for setting a second rank address from a first rank address in a memory module A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first r... | 06/03/2008 |
| 7383365 | Method and system for PCI express audiovisual output Audio and visual information processing components are co-located on a PCI Express graphics card by communicating audio and visual information received through the PCI Express interface of the graphics card to a PCI Express switch which switches audio information to... | 06/03/2008 |
| 7380095 | System and method for simulating real-mode memory access with access to extended memory In some embodiments, the invention involves a system and method relating to switching to protected mode to access extended memory while executing instruction code that is designed for real mode memory access. In at least one embodiment, the present invention is inte... | 05/27/2008 |
| 7376782 | Index/data register pair for indirect register access A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outsid... | 05/20/2008 |
| 7366797 | Data storage system with shared cache address space An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mappe... | 04/29/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7360217 | Multi-threaded packet processing engine for stateful packet processing A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to acco... | 04/15/2008 |
| 7355739 | Image forming device having a memory assignment unit An image forming device includes an operating system to execute any of a plurality of programs. The image forming device comprises a rewritable memory which has a virtual memory area managed by the operating system and an image memory area used to store image data. ... | 04/08/2008 |
| 7356627 | Device identification A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, e... | 04/08/2008 |
| 7356537 | Providing contextually sensitive tools and help content in computer-generated documents A method and system are provided for creation, implementation, and use of computer-generated “smart” documents to which functionality is attached for providing contextually sensitive tools, controls and help content to users of those documents. Portions of docum... | 04/08/2008 |
| 7353221 | Method for the automatic retrieval of engineering data of systems The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the correspondence between engineering objects and runtime objects to be de... | 04/01/2008 |
| 7340583 | Method and apparatus of controlling memory device An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an addre... | 03/04/2008 |
| 7337368 | System and method for shutdown memory testing In accordance with the teachings of the present disclosure, a system and method for reducing the amount of time for a boot operation is provided that substantially reduces disadvantages and problems associated with previously developed memory testing systems and met... | 02/26/2008 |
| 7330954 | Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the storage parameter indicates use of the information by a software proce... | 02/12/2008 |
| 7328301 | Dynamically mapping block-alterable memories In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterab... | 02/05/2008 |
| 7325194 | Method, system, and apparatus for converting numbers between measurement systems based upon semantically labeled strings Number conversion between different units of measurement in a document is enabled. A string of text entered into an application program is analyzed to determine whether it includes a number having an associated unit name. Found numbers with associated unit names are... | 01/29/2008 |
| 7325088 | Management of indexed registers in a system on a chip An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the... | 01/29/2008 |
| 7315931 | Method for managing an external memory of a microprocessor A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the address of the common area of the page pointed by a microprocessor to the p... | 01/01/2008 |
| 7310698 | Method and apparatus for extending memory addressing Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct... | 12/18/2007 |
| 7302509 | Method and data structure for random access via a bus connection A method for addressing cells in devices via an I2C bus is suggested, in which the common addressing scheme is supplemented by a ‘Data Transfer Mode’ byte. The ‘Data Transfer Mode’ byte specifies the number of the address and data bytes to follow the device ... | 11/27/2007 |
| 7296139 | In-memory table structure for virtual address translation system with translation units of variable range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 11/13/2007 |
| 7293130 | Method and system for a multi-level memory A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is... | 11/06/2007 |
| 7290078 | Serial memory comprising means for protecting an extended memory array during a write operation The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. T... | 10/30/2007 |
