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| Number | Title | Issue Date |
| 8140815 | Estimating the size of an in-memory cache This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for ea... | 03/20/2012 |
| 8086819 | Solid state drive optimizer A method for optimizing a solid state drive is described. The method involves determining whether a free space fragment on the SSD is smaller than the threshold fragment size. If the free space fragment on the SSD is smaller than the threshold fragment size, elimina... | 12/27/2011 |
| 8082415 | Estimating the size of an in-memory cache This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for ea... | 12/20/2011 |
| 8006064 | Lock-free vector utilizing a resource allocator for assigning memory exclusively to a thread Methods, systems, and articles for receiving, by a lock-free vector of a computing device, a request from a thread of the computing device to write data to the lock-free vector are described herein. In various embodiments, the lock-free vector may then determine whe... | 08/23/2011 |
| 7913053 | System and method for archival of messages in size-limited containers and separate archival of attachments in content addressable storage A method for archival of messages in content addressable storage can be provided. The method can comprise identifying a plurality of messages for archival. The identified messages can be subjected to extraction of attachments therefrom. The messages, minus any remov... | 03/22/2011 |
| 7900015 | Systems and methods of quota accounting Embodiments of the invention relate generally to incremental computing. Specifically, embodiments of the invention include systems and methods that provide for the concurrent processing of multiple, incremental changes to a data value while at the same time monitori... | 03/01/2011 |
| 7870360 | Storage area network (SAN) forecasting in a heterogeneous environment The present invention provides an approach for SAN forecasting in a heterogeneous environment. Specifically, under the present invention capacity data on the heterogeneous environment is gathered. Capacity management techniques will then be used to analyze the SAN u... | 01/11/2011 |
| 7818349 | Ultra-shared-nothing parallel database An ultra-shared-nothing parallel database system includes at least one master node and multiple slave nodes. A database consisting of at least one fact table and multiple dimension tables is partitioned and distributed across the slave nodes of the database system s... | 10/19/2010 |
| 7818534 | Determination of sampling characteristics based on available memory A portion of data records of a full input data set are imported into memory of a computer system for processing by an executing application. The full input data set includes data records of a dimensionally-modeled fact collection. An amount of the data of the full i... | 10/19/2010 |
| 7730279 | System for limiting the size of a local storage of a processor A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system runni... | 06/01/2010 |
| 7702877 | RAID stripe layout scheme A RAID storage system includes an outer stripe size that is an integer multiple J of a product of an inner stripe size and a number of data disks in a RAID disk set, where J is greater than one (1). ... | 04/20/2010 |
| 7689799 | Method and apparatus for identifying logical volumes in multiple element computer storage domains Method and apparatus for specifying and identifying logic volumes in computer systems that store logical volumes on multiple storage elements are disclosed. The logical volume identifier may be unique with respect to all other logical volumes stored on the storage e... | 03/30/2010 |
| 7533238 | Method for limiting the size of a local storage of a processor A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system runni... | 05/12/2009 |
| 7490212 | System and method for writing data to dedicated bands of a hard disk drive Data is written to a hard disk drive using shingled writing principles, i.e., each data track is partially overwritten when an immediately contiguous data track is written. Two or more contiguous data tracks establish a band, and a band may store data from one and o... | 02/10/2009 |
| 7444491 | Automatic resource sharing between FIFOs Embodiments of the present invention recite a method and system for allocating memory resources. In one embodiment, a control component coupled with a memory device determines that a data buffer adjacent to a boundary of a first FIFO queue does not contain current d... | 10/28/2008 |
| 7426625 | Data processing system and computer program product for support of system memory addresses with holes A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning ... | 09/16/2008 |
| 7409498 | Scaled coercion of disk drive capacity The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling fa... | 08/05/2008 |
| 7406579 | Selectively changeable line width memory The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficienc... | 07/29/2008 |
| 7406562 | Information read/write device An information read/write device has a first processor for instructing a second processor to write information onto or read information from a recording medium. The recording medium has a random access memory module which allows both processors to read or write data... | 07/29/2008 |
| 7403203 | Stacking series of non-power-of-two frame buffers in a memory array Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be sto... | 07/22/2008 |
| 7395403 | Simulating partition resource allocation A method, apparatus, system, and signal-bearing medium that, in an embodiment, simulate allocation of a simulated resource to simulated partitions in a simulated logically-partitioned computer and determine whether the allocation conflicts. The simulation may includ... | 07/01/2008 |
| 7394466 | Method for memory allocation for images In a method for memory allocation for images, when storing data describing an image (10) in operating memory (1), the image (10) is divided into lines, and each line is described by a separate subset of data from which at least one set of data i... | 07/01/2008 |
| 7392343 | Memory card having a storage cell and method of controlling the same A controller comprises a host interface section and a processing circuit. The host interface section receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory. The processing circuit processes the command sequence output... | 06/24/2008 |
| 7383412 | On-demand memory synchronization for peripheral systems with multiple parallel processors On-demand memory synchronization is provided for peripheral subsystems, including graphics systems, that include multiple co-processors operating in parallel. A region of master memory (memory associated with one of the peripheral co-processors) is copied, on demand... | 06/03/2008 |
| 7380093 | Storage system including a device, data management unit, control unit and/or primary computer, and method, for allocating storage area The present invention relates to a method for allocating volumes having a suitable physical location relationship based on a method of use of files by applications. When an application management unit receives an application area expansion request, a distribu... | 05/27/2008 |
| 7366819 | Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the c... | 04/29/2008 |
| 7366821 | High-speed memory system A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing ... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7360012 | Semiconductor memory device including memory controller for transmitting writing rate information to memory access device A semiconductor memory card 1 includes a user data area 21 and a management information area 22, in a data storing unit 2. According to a writing test command from a memory access device 6, a memory controller 3 writes data ... | 04/15/2008 |
| 7353350 | Data store management system and method for wireless devices In accordance with the teaching described herein, systems and methods are provided for managing memory space in a mobile device. A plurality of data storage locations may be included. A plurality of software applications may be included, with each software applicati... | 04/01/2008 |
| 7350047 | Memory overflow management Methods, systems, and media to enhance memory overflow management by identifying a memory overflow condition associated with execution of a task and adjusting memory allocation for the task to attenuate the memory overflow condition are disclosed. In particular, emb... | 03/25/2008 |
| 7350037 | Digital signal processor and digital signal processing method enabling concurrent program download and execution A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program coun... | 03/25/2008 |
| 7350045 | Dynamic memory heap tagging A data structure within a block of allocable memory of a memory structure such as a heap is used to identify the function that is responsible for causing memory problems such as random overwrites, buffer overruns, double or multiple “frees,” and the like. The da... | 03/25/2008 |
| 7343451 | Disk array device and remote copying control method for disk array device Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote co... | 03/11/2008 |
| 7342816 | Daisy chainable memory chip A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip res... | 03/11/2008 |
| 7339837 | Configurable embedded processor A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support differen... | 03/04/2008 |
| 7340537 | Memory channel with redundant presence detect A memory agent may include a link interface having bit lanes and may utilize more than one bit lane to determine if another memory agent is also connected to the same link interface. ... | 03/04/2008 |
| 7337285 | Buffer allocation based upon priority An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer... | 02/26/2008 |
| 7337273 | Strategies for reading information from a mass storage medium using a cache memory Cache management strategies are described for retrieving information from a storage medium, such as an optical disc, using a cache memory including multiple cache segments. A first group of cache segments can be devoted to handling the streaming transfer of a first ... | 02/26/2008 |
| 7330957 | User-based allocation and deallocation of storage in a storage system A management server includes the user management segment information having stored therein a volume managed by a user, a receiving unit for receiving a volume allocation request from a management computer, a sending unit for sending the volume allocation request to ... | 02/12/2008 |
