Famous Patents
3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8151075 | Multiple access type memory and method of operation A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response ... | 04/03/2012 |
| 8122218 | Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control sign... | 02/21/2012 |
| 8112604 | Tracking load store ordering hazards A method and system for processing data. In one embodiment, the method includes receiving a plurality of stores into a store queue, where each store is a result from a processor, and where the plurality of stores are destined for at least one memory address. The met... | 02/07/2012 |
| 8086815 | System for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 12/27/2011 |
| 8078821 | Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control sign... | 12/13/2011 |
| 8060721 | Apparatus and method for a synchronous multi-port memory A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditiona... | 11/15/2011 |
| 8055872 | Data processor with hardware accelerator, accelerator interface and shared memory management unit A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware... | 11/08/2011 |
| 7941627 | Specialized memory move barrier operations An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently rec... | 05/10/2011 |
| 7908452 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 03/15/2011 |
| 7877566 | Simultaneous pipelined read with multiple level cache for improved system performance using flash technology A read command protocol and a method of accessing a nonvolatile memory device having an internal cache memory. A memory device configured to accept a first and second read command, outputting a first requested data while simultaneously reading a second requested dat... | 01/25/2011 |
| 7865685 | Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control sign... | 01/04/2011 |
| 7716444 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 05/11/2010 |
| 7681004 | Advanced dynamic disk memory module Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory... | 03/16/2010 |
| 7657723 | System and method for processor with predictive memory retrieval assist A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the ... | 02/02/2010 |
| 7653795 | Control of metastability in the pipelined data processing apparatus A method and integrated circuit for accessing data in a pipelined data processing apparatus in which the operating conditions of the pipelined data processing apparatus are such that metastable signals may occur on at least the boundaries of the pipelined stages is ... | 01/26/2010 |
| 7634631 | Method and system for updating network flow statistics stored in an external memory A method for updating a current network flow statistic stored in a memory device, comprising: storing a first statistic and a first address corresponding to a location in the memory device in a first stage of a multiple stage delay pipeline; shifting the first stati... | 12/15/2009 |
| 7603535 | Low power consumption semiconductor memory device capable of selectively changing input/output data width and data input/output method A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of... | 10/13/2009 |
| 7603536 | Data processing apparatus and image reading apparatus A data processing apparatus includes a data processing section that issues a plurality of data transfer requests simultaneously; an internal memory provided inside a circuit including the data processing section; an internal memory control section that performs an a... | 10/13/2009 |
| 7509469 | Semiconductor memory asynchronous pipeline An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control sign... | 03/24/2009 |
| 7490210 | System and method for processor with predictive memory retrieval assist A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the ... | 02/10/2009 |
| 7487318 | Managing write-to-read turnarounds in an early read after write memory system Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a s... | 02/03/2009 |
| 7478215 | Multi-controller write operations A system and method for high performance multi-controller processing is disclosed. Independent Network storage controllers (NSCs) are connected by a high-speed data link. The NSCs control a plurality of storage devices. connected by a Fiber Channel Arbitrated Loop (... | 01/13/2009 |
| 7464242 | Method of load/store dependencies detection with dynamically changing address length A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline a... | 12/09/2008 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7426621 | Memory access request arbitration A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the ... | 09/16/2008 |
| 7421559 | Apparatus and method for a synchronous multi-port memory A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also inc... | 09/02/2008 |
| 7421548 | Memory system and method for two step memory write operations A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation... | 09/02/2008 |
| 7421557 | Method and device for performing cache reading Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. ... | 09/02/2008 |
| 7418537 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 08/26/2008 |
| 7418540 | Memory controller with command queue look-ahead In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in ... | 08/26/2008 |
| 7418543 | Processor having content addressable memory with command ordering A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands. ... | 08/26/2008 |
| 7409516 | Pending request scoreboard for out-of-order memory scheduler Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count dow... | 08/05/2008 |
| 7395399 | Control circuit to enable high data rate access to a DRAM with a plurality of areas A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for dete... | 07/01/2008 |
| 7392362 | System and method for volume management A volume management system includes a management server which includes a memory and a processor, the memory stores an area level indicative of released or unreleased, a priority level indicative of a priority for establishing a redundancy, a use status indicative of... | 06/24/2008 |
| 7383409 | Cache systems and methods for employing speculative fills One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comp... | 06/03/2008 |
| 7380084 | Dynamic detection of block boundaries on memory reads In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the ce... | 05/27/2008 |
| 7376950 | Signal aggregation The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operatio... | 05/20/2008 |
| 7376793 | Cache coherence protocol with speculative writestream A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operati... | 05/20/2008 |
| 7373460 | Media drive and command execution method thereof Embodiments of the present invention provide a media drive capable of improving command processing performance by, when a plurality of commands is queued, shortening seek time and rotational latency, and also effectively making use of the shortened period of time. I... | 05/13/2008 |
| 7373490 | Emptying packed data state during execution of packed data instructions A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instr... | 05/13/2008 |
