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| Number | Title | Issue Date |
| 8078820 | Managing message queues A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, de... | 12/13/2011 |
| 8051266 | Automatic memory management (AMM) The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident... | 11/01/2011 |
| 8028144 | Memory module with reduced access granularity A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path... | 09/27/2011 |
| 8010767 | Synchronous flash memory with status burst output A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an exte... | 08/30/2011 |
| 8010766 | Increasing buffer locality during multiple table access operations Disclosed are a method, information processing system, and computer readable medium for managing table scan processes. The method includes monitoring a plurality of storage medium table scan processes. Each storage medium table scan process in the plurality of stora... | 08/30/2011 |
| 7966469 | Memory system and method for operating a memory system A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second ... | 06/21/2011 |
| 7949844 | Pipelined burst memory access A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation. ... | 05/24/2011 |
| 7945755 | Independent link and bank selection Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controller... | 05/17/2011 |
| 7921272 | Monitoring patterns of processes accessing addresses in a storage device to determine access parameters to apply Provided are a method, system, and article of manufacture for monitoring patterns of processes accessing addresses in a storage device to determine access parameters to apply. Processes accessing addresses of data in a storage device are monitored. The processes are... | 04/05/2011 |
| 7865684 | Managing message queues A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, de... | 01/04/2011 |
| 7849283 | Linear combiner weight memory A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weigh... | 12/07/2010 |
| 7818712 | Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr... | 10/19/2010 |
| 7752411 | Chips providing single and consolidated commands In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first ... | 07/06/2010 |
| 7747833 | Independent link and bank selection Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controller... | 06/29/2010 |
| 7739470 | Limit algorithm using queue depth to control application performance Described are techniques for controlling performance of a data storage system. A performance goal specifying a limit for an I/O class is received. A number of requests of the I/O class to be processed concurrently to achieve the performance goal so that an observed ... | 06/15/2010 |
| 7730276 | Striping of data into memory of a network data switch to prevent read and write collisions A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based o... | 06/01/2010 |
| 7711918 | Apparatus and method for operating flash memory according to priority order Provided is an apparatus and method for operating a flash memory according to a priority order, in which a fast response is insured. The apparatus includes a time calculation unit which calculates an operation execution time required to perform a first operation, a ... | 05/04/2010 |
| 7694099 | Memory controller having an interface for providing a connection to a plurality of memory devices A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data ... | 04/06/2010 |
| 7673111 | Memory system with both single and consolidated commands In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in re... | 03/02/2010 |
| 7640414 | Method and apparatus for forwarding store data to loads in a pipelined processor Methods, systems, and computer program products for forwarding store data to loads in a pipelined processor are provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units ope... | 12/29/2009 |
| 7603534 | Synchronous flash memory with status burst output A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an exte... | 10/13/2009 |
| 7594089 | Smart memory based synchronization controller for a multi-threaded multiprocessor SoC A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one ... | 09/22/2009 |
| 7558933 | Synchronous dynamic random access memory interface and method A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The... | 07/07/2009 |
| 7558934 | Data storage unit, data storage controlling apparatus and method, and data storage controlling program A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage... | 07/07/2009 |
| 7533232 | Accessing data from different memory locations in the same cycle In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cy... | 05/12/2009 |
| 7526626 | Memory controller configurable to allow bandwidth/latency tradeoff A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coup... | 04/28/2009 |
| 7487316 | Archive and restore system and methodology for on-line edits utilizing non-volatile buffering The present invention relates to a system and methodology to mitigate memory current requirements in an industrial controller and to facilitate efficient on-line editing, storage and retrieval of user programs and data. A segmented memory architecture is provided, w... | 02/03/2009 |
| 7487317 | Cache-aware scheduling for a chip multithreading processor A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executi... | 02/03/2009 |
| 7475210 | Data stream generation method for enabling high-speed memory access An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocate... | 01/06/2009 |
| 7464241 | Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that ... | 12/09/2008 |
| 7444479 | Fully buffered DIMM read data substitution for write acknowledgement A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue. ... | 10/28/2008 |
| 7444634 | Method and apparatus for providing dynamic locks for global resources One embodiment of the present invention provides a system that facilitates applying a dynamic lock to a range of a resource within a computer system. Upon receiving a request to lock to the range of the resource from a thread, the system examines an active lock pool... | 10/28/2008 |
| 7444466 | Implementing feedback directed deferral of nonessential DASD operations A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a bu... | 10/28/2008 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7441094 | Memory management configuration Memory management within a runtime execution environment may be configured in accordance with data associated with executable code loaded therein. ... | 10/21/2008 |
| 7437511 | Secondary level cache for storage area networks For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer includes the local caches coupled together, the local caches individu... | 10/14/2008 |
| 7433904 | Buffer memory management Various systems and methods for buffer memory management are disclosed. In one embodiment a buffer memory includes at least one queue configured to store a number of buffer access tasks. Buffer reclamation logic is executed to free at least one segment of the buffer... | 10/07/2008 |
| 7433996 | System and method for refreshing random access memory cells A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request ... | 10/07/2008 |
| 7426620 | Apparatus and method for memory access of sharing buses An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's default... | 09/16/2008 |
| 7426621 | Memory access request arbitration A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the ... | 09/16/2008 |
