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| Number | Title | Issue Date |
| 8185711 | Memory module, a memory system including a memory controller and a memory module and methods thereof A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may i... | 05/22/2012 |
| 8185714 | Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data regi... | 05/22/2012 |
| 8185712 | System and method for intelligent storage migration The present invention relates to a methodology and computer program product for data storage migration that comprises monitoring a plurality of entities that comprise a storage area network for a predetermined set of information gathering cycles, constructing a reso... | 05/22/2012 |
| 8185713 | Flexible sequencer design architecture for solid state memory controller A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be c... | 05/22/2012 |
| 8166268 | Memory command delay balancing in a daisy-chained memory topology A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIM... | 04/24/2012 |
| 8145867 | Non-volatile memory devices for outputting data using double data rate (DDR) operations and methods of operating the same A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchroniza... | 03/27/2012 |
| 8145868 | Method and system for providing frame start indication in a memory system having indeterminate read data latency A method and system for providing frame start indication in a memory system having indeterminate read data latency. The method includes receiving a data transfer and determining if the data transfer includes a frame start indicator. The method also includes capturin... | 03/27/2012 |
| 8140803 | Structure for reducing latency associated with read operations in a memory system A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communicat... | 03/20/2012 |
| 8140804 | Systems and methods for determining whether to perform a computing operation that is optimized for a specific storage-device-technology type A computer-implemented method for determining whether to perform a computing operation that is optimized for a specific storage-device-technology type may comprise: 1) performing at least one proximate read operation by accessing a control location on a storage devi... | 03/20/2012 |
| 8140805 | Memory component having write operation with multiple time periods A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A d... | 03/20/2012 |
| 8131967 | Asynchronous data interface An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock ... | 03/06/2012 |
| 8131968 | Information processing device An information processing device in which memory bands can be significantly cut. In the present device, an access determining/managing portion (105) determines whether or not write data meets access determination conditions when write-accessing a memory (1... | 03/06/2012 |
| 8126846 | System and method for replicating data According to the present invention, techniques for controlling copying of logical volumes within a computer storage system are provided. A representative embodiment includes a plurality of storage devices controlled by a control unit, one or more processors, and a b... | 02/28/2012 |
| 8117415 | Storage device estimating a completion time for a storage operation A storage device or system provides to a host processor an estimation of a completion time of a storage operation. The completion time may be based on the duration of automatic storage operations, which are not administered by the host processor. The storage device ... | 02/14/2012 |
| 8108643 | Semiconductor memory chip and memory system In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first... | 01/31/2012 |
| 8095762 | Low latency synchronous memory performance switching with drift refresh A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous ... | 01/10/2012 |
| 8095763 | Method for reducing latency in a raid memory system while maintaining data integrity A latency reduction method for read operations of an array of N disk storage devices (210) having n disk storage devices (210A-210H) for data storage and p of disk storage devices (210I, 210J) for storing parity data is provided. U... | 01/10/2012 |
| 8095761 | Low latency synchronous memory performance switching A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous ... | 01/10/2012 |
| 8086814 | Semiconductor integrated circuit apparatus A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock gen... | 12/27/2011 |
| 8086812 | Transceiver with latency alignment circuitry In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmi... | 12/27/2011 |
| 8086813 | Synchronous memory read data capture A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The cont... | 12/27/2011 |
| 8082413 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode... | 12/20/2011 |
| 8074040 | Flash device and method for improving performance of flash device The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access... | 12/06/2011 |
| 8069327 | Commands scheduled for frequency mismatch bubbles In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the... | 11/29/2011 |
| 8055871 | Low latency synchronous memory performance switching using update control A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous ... | 11/08/2011 |
| 8046559 | Memory rank burst scheduling A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The meth... | 10/25/2011 |
| 8046558 | File system having predictable real-time performance A file system that permits predictable accesses to file data stored on devices that may have a variable access latency dependent on the physical location of the file on the physical storage device. A variety of features that guarantee timely, real-time response to I... | 10/25/2011 |
| 8041682 | Storage control system and method A disk array system including a plurality of disk drives, including: a plurality of first-type disk drives being used to form a first-type logical unit having a plurality of a first-type of chunks; a plurality of second-type disk drives being used to form a second-t... | 10/18/2011 |
| 8037272 | Structure for memory chip for high capacity memory subsystem supporting multiple speed bus A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interf... | 10/11/2011 |
| 8028143 | Method and apparatus for transmitting memory pre-fetch commands on a bus A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to... | 09/27/2011 |
| 8024540 | Integrated memory control apparatus An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the s... | 09/20/2011 |
| 8019957 | Method and system for automatic calibration of a DQS signal in a storage controller A calibration module for a data storage control system. The calibration system includes a programmable delay module configured to i) receive a data strobe signal, ii) receive a delay value, and iii) output a delayed data strobe signal to a buffer based on the delay ... | 09/13/2011 |
| 8019958 | Memory write signaling and methods thereof In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to ... | 09/13/2011 |
| 8015382 | Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data regi... | 09/06/2011 |
| 8010765 | Semiconductor memory device and method for controlling clock latency according to reordering of burst data In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The contr... | 08/30/2011 |
| 8006057 | Memory devices with buffered command address bus Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between ... | 08/23/2011 |
| 7996642 | Digital locked loop on channel tagged memory requests for memory optimization A method and system for performing memory optimization. The method includes receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the r... | 08/09/2011 |
| 7996641 | Structure for hub for supporting high capacity memory subsystem A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved s... | 08/09/2011 |
| 7991975 | Storage medium control unit, data storage device, data storage system, method, and control program To prevent random access commands from remaining even in the case of mixed sequential and random accesses. A storage medium control unit is used in a data storage device adapted to perform processing on a data storage medium based on multiple requests including sequ... | 08/02/2011 |
| 7987332 | Methods for storing memory operations in a queue A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the ... | 07/26/2011 |
