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| Number | Title | Issue Date |
| 8099567 | Reactive placement controller for interfacing with banked memory storage An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is inc... | 01/17/2012 |
| 8078811 | Method for digital storage of data on a data memory with limited available storage space The most important data in a first memory of a data processing system are stored in a limited second data memory given upon a transfer thereof. The demarcation between important (and still storable) data on the one hand and less important (and therefore no longer st... | 12/13/2011 |
| 8037261 | Closed-loop system for dynamically distributing memory bandwidth A closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components is provided. Specifically, the present invention includes monitors for measuring a performance of each of the real-time components. Based on ... | 10/11/2011 |
| 8032723 | Methods and mechanisms for proactive memory management A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed.... | 10/04/2011 |
| 8001338 | Multi-level DRAM controller to manage access to DRAM Providing for multi-tiered RAM control is provided herein. As an example, a RAM access management system can include multiple input controllers each having a request buffer and request scheduler. Furthermore, a request buffer associated with a controller can vary in... | 08/16/2011 |
| 7962706 | Methods and systems for improving read performance in data de-duplication storage The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a data de-duplication system that retrieves d... | 06/14/2011 |
| 7958324 | Computer system and command execution frequency control method A computer system of the present invention can adjust the execution frequencies of a command issued from a host and a command issued from a storage. An external manager disposed in the host configures a priority for a host command issued from a command issuing modul... | 06/07/2011 |
| 7921266 | System and method of accessing memory within an information handling system A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operati... | 04/05/2011 |
| 7900001 | System and method for obscuring hand-held device data traffic information Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that... | 03/01/2011 |
| 7882314 | Efficient scheduling of background scrub commands A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. ... | 02/01/2011 |
| 7877558 | Memory controller prioritization scheme A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the f... | 01/25/2011 |
| 7873801 | Partitionable accounting of memory utilization Managing physical memory for one or more processes with both a minimum and a maximum amount of physical memory. Memory sets are created, each specifying a number of credits. The total number of credits specified by all memory sets are equal to the total number of pa... | 01/18/2011 |
| 7853760 | Advanced memory management architecture for large data volumes A method for managing a memory system for large data volumes includes providing a central memory management system comprising a memory management interface between applications and a memory of a programmed computer, maintaining a global priority list of data buffers... | 12/14/2010 |
| 7853761 | Classifying write commands into groups based on cumulated flush time According to one embodiment, a magnetic disk apparatus comprises a volatile memory for storing write commands and data accompanying the commands supplied from a host system, and a flush control unit for classifying the write commands into a first group of commands a... | 12/14/2010 |
| 7849277 | Bank controller, information processing device, imaging device, and controlling method A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priori... | 12/07/2010 |
| 7818519 | Timeslot arbitration scheme A method for arbitrating between a plurality of access requests issued in relation to a resource by a plurality of requestors, wherein each request can be one of at least two types, a first of the types having a higher latency associated with its performance than at... | 10/19/2010 |
| 7818520 | Method of specifying access sequence of a storage device The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to ... | 10/19/2010 |
| 7818521 | Memory management for a mobile multimedia processor Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests. The plurality of memory requests may be... | 10/19/2010 |
| 7802065 | Peer to peer based cache management A system for managing a local cache that is part of a distributed cache is disclosed. The system includes a computing device. The computing device includes or is in electronic communication with a computer-readable medium. The computer-readable medium includes execu... | 09/21/2010 |
| 7802066 | Advanced memory management architecture for large data volumes An efficient memory management method for handling large data volumes, comprising a memory management interface between a plurality of applications and a physical memory, determining a priority list of buffers accessed by the plurality of applications, providing eff... | 09/21/2010 |
| 7774563 | Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests A computer-implemented method, data processing system, and computer usable program code are provided for reducing memory access latency. A memory controller receives a memory access request and determines if an address associated with the memory access request falls... | 08/10/2010 |
| 7769970 | Unified memory controller A unified memory controller (UMC) is disclosed. The UMC may be used in a digital television (DTV) receiver. The UMC allows the DTV receiver to use a unified memory. The UMC accepts memory requests from various clients, and determines which requests should receive pr... | 08/03/2010 |
| 7752400 | Arbitration and crossbar device and method Disclosed is a method and apparatus for crossbar arbitration. In one embodiment, the crossbar arbitration includes a memory, a plurality of functional units that transfer data to and from the memory, a crossbar unit that provides a data path from each unit to the me... | 07/06/2010 |
| 7739461 | DRAM power management in a memory controller A memory controller uses a power- and performance-aware scheduler which reorders memory commands based on power priorities. Selected memory ranks of the memory device are then powered down based on rank localities of the reordered commands. The highest power priorit... | 06/15/2010 |
| 7698514 | Data processing system and method for interconnect arbitration A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via th... | 04/13/2010 |
| 7698513 | Methods and mechanisms for proactive memory management A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed.... | 04/13/2010 |
| 7664922 | Data transfer arbitration apparatus and data transfer arbitration method When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 seque... | 02/16/2010 |
| 7660952 | Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a ... | 02/09/2010 |
| 7644241 | Data processing apparatus, and the control method, program, and storage medium thereof History information of storage destinations designated for storing data input to an image processing device is managed. The priorities of a plurality of storage areas which are storage destination candidates are determined based on the managed history information. T... | 01/05/2010 |
| 7634623 | Method and apparatus for self-timed data ordering for multi-data rate memories and system incorporating same A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the succes... | 12/15/2009 |
| 7610458 | Data processing system, processor and method of data processing that support memory access according to diverse memory models A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing syste... | 10/27/2009 |
| 7603527 | Resolving false dependencies of speculative load instructions Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load operation and a store operation are compared in response to a determin... | 10/13/2009 |
| 7574573 | Reactive placement controller for interfacing with banked memory storage An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is inc... | 08/11/2009 |
| 7565498 | System and method for maintaining write order fidelity in a distributed environment Various systems and methods for maintaining write order fidelity in a distributed environment are disclosed. One method, which can be performed by each node in a cluster, involves associating a current sequence number with each of several write operations included i... | 07/21/2009 |
| 7565497 | Coarse write barrier control mechanism A method for a coarse write barrier control mechanism comprises maintaining a control table comprising a plurality of entries, where each entry may include an encoding of a write barrier function associated with a corresponding region of a heap. In response to a det... | 07/21/2009 |
| 7543122 | System and method for obscuring hand-held device data traffic information Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that... | 06/02/2009 |
| 7533227 | Method for priority scheduling and priority dispatching of store conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an addit... | 05/12/2009 |
| 7512753 | Disk array control apparatus and method A disk array control apparatus determines-whether or not a I/O process request from a host computer is causing a cache hit at a disk cache memory. The apparatus identifies the I/O process request as either high priority task or low priority task. The apparatus calcu... | 03/31/2009 |
| 7512754 | System and method for optimizing storage utilization In a storage area network, the storage pool is the principal component that determines the storage quality of service in the network. The proposed system's goal is to balance the utilizations of the storage pools using a suitable metric (e.g., standard deviation). T... | 03/31/2009 |
| 7506114 | Data transfer device which executes DMA transfer, semiconductor integrated circuit device and data transfer method A data transfer device which controls data transfer between a first memory device and a second memory device, includes a first transfer arbiter circuit and a second transfer arbiter circuit. The first transfer arbiter circuit outputs, in response to a transfer instr... | 03/17/2009 |
