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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8135926 | Cache-based control of atomic operations in conjunction with an external ALU block One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the nece... | 03/13/2012 |
| 8121994 | Partially embedded database and an embedded database manager for a control system A method is used for editing a data element stored in a static memory device comprising a plurality of storage units. The method includes a step of copying a content of one of the storage units to a dynamic memory device, wherein the content comprises the data eleme... | 02/21/2012 |
| 8112595 | Command cancellation channel for read—modify—write operation in a memory Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first m... | 02/07/2012 |
| 8103903 | Read-modify-write protocol for maintaining parity coherency in a write-back distributed redundancy data storage system Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes, each node comprising a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe includi... | 01/24/2012 |
| 8065495 | Apparatus, method and computer program for processing information An information processing apparatus for recording data onto a recording medium, includes an access controller for outputting, to a medium-specific controller, record data input from an application and directed to the recording medium. The access controller performs ... | 11/22/2011 |
| 8024533 | Host memory interface for a parallel processor A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the... | 09/20/2011 |
| 7908443 | Memory controller and method for optimized read/modify/write performance A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embo... | 03/15/2011 |
| 7889569 | System, method and storage medium for controlling asynchronous updates to a register A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The pr... | 02/15/2011 |
| 7870350 | Write buffer for read-write interlocks A write buffer for read-write interlocks improves memory access performance by minimizing the latency needed to avoid a read-after-write hazard when a read follows a write to the same memory location. Rather than waiting until a write has been stored in the memory l... | 01/11/2011 |
| 7870351 | System, apparatus, and method for modifying the order of memory accesses Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines ... | 01/11/2011 |
| 7849276 | Host memory interface for a parallel processor A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the... | 12/07/2010 |
| 7739460 | Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-b... | 06/15/2010 |
| 7716430 | Separate handling of read and write of read-modify-write Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to writ... | 05/11/2010 |
| 7680992 | Read-modify-write memory with low latency for critical requests A memory interface permits a read-modify-write process to be implemented as an interruptible process. A pending read-modify-write is capable of being temporarily interrupted to service a higher priority memory request. ... | 03/16/2010 |
| 7676639 | Separate handling of read and write of read-modify-write Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to writ... | 03/09/2010 |
| 7627723 | Atomic memory operators in a parallel processor Methods, apparatuses, and systems are presented for updating data in memory while executing multiple threads of instructions, involving receiving a single instruction from one of a plurality of concurrently executing threads of instructions, in response to the singl... | 12/01/2009 |
| 7584336 | Systems and methods for providing data modification operations in memory subsystems Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller recei... | 09/01/2009 |
| 7509463 | Cell processor atomic compare and swap using dedicated synergistic processor element An atomic compare and swap operation that can be implemented in processor system having a power processor element (PPE) and a synergistic processor element (SPE) that have different sized memory transfer capabilities. The PPE notifies an SPE to perform a compare and... | 03/24/2009 |
| 7475202 | Memory controller and method for optimized read/modify/write performance A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embo... | 01/06/2009 |
| 7444460 | Data storage device, method for updating management information in data storage device, and computer program The invention provides a data storage device and a method of updating management information, capable of dealing with management information in a highly reliable manner so that information is not easily lost when an error occurs. File management information such as ... | 10/28/2008 |
| 7430572 | Storage control system and method A disk array system including a plurality of disk drives, including a plurality of first-type disk drives having a first predetermined level of reliability and used to form a first-type logical unit having a plurality of a first-type of chunks, and a plurality of se... | 09/30/2008 |
| 7428625 | Method of adaptively controlling data access by data storage system and disk drive using the method A method of adaptively controlling data access by a data storage system, in which the sizes and the number of read/write caches are adjusted according to the size of a data access unit, and a disk drive using the method. The method of adaptively controlling read acc... | 09/23/2008 |
| 7424581 | Host memory interface for a parallel processor A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the... | 09/09/2008 |
| 7418543 | Processor having content addressable memory with command ordering A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands. ... | 08/26/2008 |
| 7401191 | System and method for performing disk write operations by writing to a data depot prior to an in-place write Methods, computer programs, information handling systems, and state machines for performing an atomic write to a data block area are disclosed. The atomic write is an in-place write> The method includes receiving one or more data blocks to write to the data block ar... | 07/15/2008 |
| 7392346 | Memory updater using a control array to defer memory operations A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations. First, a control array is provided. The control array is associated wit... | 06/24/2008 |
| 7389392 | Chip processors with integrated I/O A solution to the read-modify-write problem for mixed tri-state chip processors by implementing a simple hardware change. This change could easily be built into microcontrollers and other chip processors to once and for all solve the problem. The present invention u... | 06/17/2008 |
| 7380111 | Out-of-order processing with predicate prediction and validation with correct RMW partial write new predicate register values A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. T... | 05/27/2008 |
| 7380076 | Information processing apparatus and method of accessing memory The present invention makes it possible to inexpensively and quickly execute a process of rewriting data stored in a memory, thus reducing the power consumption of an information processing apparatus. In connection with a conventional Read-Modify-Write function, an ... | 05/27/2008 |
| 7380077 | System, method and storage medium for controlling asynchronous updates to a register A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The pr... | 05/27/2008 |
| 7363442 | Separate handling of read and write of read-modify-write A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RM... | 04/22/2008 |
| 7360032 | Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache ... | 04/15/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7353445 | Cache error handling in a multithreaded/multi-core processor In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the c... | 04/01/2008 |
| 7343456 | Load-linked/store conditional mechanism in a CC-NUMA system A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a ... | 03/11/2008 |
| 7333581 | Method of processing data for a decoding operation using windows of data The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of writing a current window of data into a unique buffer (BUF) in a first ... | 02/19/2008 |
| 7334080 | Nonvolatile memory with independent access capability to associated buffer A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer ... | 02/19/2008 |
| 7330908 | System and method for processing packets using location and content addressable memories An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the app... | 02/12/2008 |
| 7328317 | Memory controller and method for optimized read/modify/write performance A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embo... | 02/05/2008 |
| 7321955 | Control device, control method and storage medium recording a control program for controlling write-back schedule of data from cache memory to a plurality of storage devices The storage control device of the present invention controls a plurality of storage devices. The storage control device comprises an LRU write-back unit writing back data stored in the cache memory of the storage control device into the plurality of storage devices ... | 01/22/2008 |
