Class 711/151 - Prioritized access regulation

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter including provisions for assigning priority
No. of patents: 1005
Last issue date: 05/15/2012

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Number	Title	Issue Date
8180975	Controlling interference in shared memory systems using parallelism-aware batch scheduling A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “reque...	05/15/2012
8145853	Semiconductor memory apparatus, memory access control system and data reading method In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores ...	03/27/2012
8135919	Operation control of a shared memory partitioned into multiple storage areas A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quant...	03/13/2012
8131949	Memory access control device equipped with memory access request generating modules/arbitrator and control method thereof A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory ac...	03/06/2012
8131950	Low latency request dispatcher A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of ...	03/06/2012
8103837	Servicing memory read requests Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the ty...	01/24/2012
8099562	Scalable interface for a memory array A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority ...	01/17/2012
8099563	Storage device and access instruction sending method A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the...	01/17/2012
8095744	Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections d...	01/10/2012
8074031	Multi-processor circuit with shared memory banks A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to address...	12/06/2011
8010752	Performing initialization for non access-selected memory device supporting multimediacard (MMC) interface A storage interfacing method and apparatus for a mobile terminal are disclosed. The storage interfacing method utilizes a plurality of storage devices. The method includes identifying the storage devices, detecting an occurrence of an access request event to one of ...	08/30/2011
8001335	Low latency request dispatcher A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of ...	08/16/2011
7917706	SDRAM controller A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one o...	03/29/2011
7899998	Conflict avoidance in data store replication A conflict avoidance system is provided. The conflict avoidance system comprises a first data store provided at a first geographic location and a second data store at a second geographic location, where the first and second data stores are replications of one anothe...	03/01/2011
7890708	Prioritization of out-of-order data transfers on shared data bus Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers ...	02/15/2011
7882311	Non-snoop read/write operations in a system supporting snooping Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting ...	02/01/2011
7873797	Memory controller The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command schedule...	01/18/2011
7870347	Data processing system The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of ...	01/11/2011
7831639	System and method for providing data protection by using sparse files to represent images of data stored in block devices Various systems and methods are disclosed for storing one or more point-in-time images of data stored in a block device in a sparse file. In one embodiment, a method involves identifying a block of data within a block device and copying the block of data to a sparse...	11/09/2010
7831780	Operating system supplemental disk caching system and method A computer system utilizes subsystem supplemental memory resources to implement operating system supplemental disk caching. A main system processor (e.g., a central processing unit) processes information associated with main system functions. A bulk memory (e.g., a ...	11/09/2010
7822930	Balanced allocation of multiple resources, or of multiple resources from multiple providers A system calculates the optimal allocation of two or more resources provided by a resource provider to a task within a computer system from a plurality of possible allocations. In doing so, the system calculates the total volume of an N-dimensional cube, where N is ...	10/26/2010
7818514	Low latency memory access and synchronization A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchr...	10/19/2010
7814283	Low latency request dispatcher A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of ...	10/12/2010
7809897	Managing lock rankings Methods of monitoring a computer system. The methods may comprise the steps of calculating a first checksum of a data location and receiving a request from an operation running on the computer system for a lock corresponding to the data location. The methods may als...	10/05/2010
7809896	Efficient sharing of memory between applications running under different operating systems on a shared hardware system A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution...	10/05/2010
7809895	Low overhead access to shared on-chip hardware accelerator with memory-based interfaces In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or mor...	10/05/2010
7805577	Managing memory access in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	09/28/2010
7783844	Shared/exclusive control scheme among sites including storage device system shared by plural high-rank apparatuses, and computer system equipped with the same control scheme In a computer system where a site including a storage device system connected to high-rank apparatuses, via a network such as a SAN, and a site including a storage device system similarly connected to high-rank apparatuses via a network are connected to each other v...	08/24/2010
7761669	Memory controller granular read queue dynamic optimization of command selection A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests a...	07/20/2010
7734879	Efficiently boosting priority of read-copy update readers in a real-time data processing system A technique for efficiently boosting the priority of a preemptable data reader in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no lo...	06/08/2010
7707364	Non-snoop read/write operations in a system supporting snooping Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting ...	04/27/2010
7689781	Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group The invention relates to a functional system comprising a set of functions (F, F′) which are to access a collective resource (RSRC), the system including an interface (INT) arranged to implement an access scheme (AS) including at least one state (I) defined by an ...	03/30/2010
7685374	Multi-interface and multi-bus structured solid-state storage subsystem A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may s...	03/23/2010
7657712	Microprocessor architecture capable of supporting multiple heterogeneous processors A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the on...	02/02/2010
7657711	Dynamic memory bandwidth allocation A memory bandwidth control device for improving efficiency of data transfer between an external device and a memory. A memory is used for temporarily storing and outputting data to be communicated with external devices being connected via input/output ports, and an ...	02/02/2010
7647455	Information processing apparatus and method, program, and program recording medium An information processing apparatus for processing an access request to access a recording medium from an application includes the following elements. A setting unit sets a priority unique to the access request from the application or permission information indicati...	01/12/2010
7634622	Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to ban...	12/15/2009
7606983	Sequential ordering of transactions in digital systems with multiple requestors A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, ...	10/20/2009
7562195	Balanced allocation of multiple resources, or of multiple resources from multiple providers A system calculates the optimal allocation of two or more resources provided by a resource provider to a task within a computer system from a plurality of possible allocations. In doing so, the system calculates the total volume of an N-dimensional cube, where N is ...	07/14/2009
7562196	Method and apparatus for determining precedence in a classification engine A precedence determination system including a first type memory bank configured to receive a first search signal and to provide first search result indications, a second type memory bank configured to receive a second search signal and to provide second search resul...	07/14/2009

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Class 711/151 - Prioritized access regulation