Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8190829 | Data processing circuit with multiplexed memory A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for... | 05/29/2012 |
| 8185703 | Detection and control of resource congestion by a number of processors In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion de... | 05/22/2012 |
| 8176265 | Shared single-access memory with management of multiple parallel requests A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a ... | 05/08/2012 |
| 8171235 | Atomic compare and swap using dedicated processor An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on a... | 05/01/2012 |
| 8166255 | Reservation required transactions A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transa... | 04/24/2012 |
| 8145852 | Device having shared memory and method for providing access status information by shared memory A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its ... | 03/27/2012 |
| 8117403 | Transactional memory system which employs thread assists using address history tables A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table an... | 02/14/2012 |
| 8112591 | System and method for detection of non-deterministic memory access events A concurrent and asynchronous system may be managed by monitoring the performance of a plurality of operations that access a designated region of memory. In that region of memory, an occurrence of a potentially non-deterministic event can be detected when at least o... | 02/07/2012 |
| 8108625 | Shared memory with parallel access and access conflict resolution mechanism Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can b... | 01/31/2012 |
| 8108626 | Apparatus and method of time keeping for non-real-time operating system An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a ... | 01/31/2012 |
| 8099561 | Shared memory system for a tightly-coupled multiprocessor A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical ... | 01/17/2012 |
| 8086805 | Advanced contention detection A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the ... | 12/27/2011 |
| 8065489 | Method and apparatus for managing concurrent access among computers to a bitmap stored on disk storage Method and apparatus for managing concurrent access among computers to a bitmap stored on disk storage. In some examples, a command is received from a requesting computer of the computers, the command indicating that one or more bits in the bitmap are to be cleared.... | 11/22/2011 |
| 8055855 | Varying access parameters for processes to access memory addresses in response to detecting a condition related to a pattern of processes access to memory addresses Provided are a method, system, and article of manufacture for varying access parameters for processes to access memory addresses in response to detecting a condition related to a pattern of processes access to memory addresses. A monitored condition is detected duri... | 11/08/2011 |
| 8028132 | Collision handling apparatus and method The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads ( | 09/27/2011 |
| 8006042 | Floating point bypass retry A system and method for increasing the throughput of a processor during cache misses. During the retrieval of the cache miss data, subsequent memory requests are generated and allowed to proceed to the cache. The data for the subsequent cache hits are stored in a by... | 08/23/2011 |
| 7991967 | Using type stability to facilitate contention management Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is ... | 08/02/2011 |
| 7971005 | Advanced contention detection A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the ... | 06/28/2011 |
| 7962699 | Concurrent execution of critical sections by eliding ownership of locks One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without... | 06/14/2011 |
| 7958321 | Apparatus and method for reducing memory access conflict Provided are an apparatus and a method of reducing memory access conflict. An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a ... | 06/07/2011 |
| 7949837 | Contention detection and resolution A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the ... | 05/24/2011 |
| 7949836 | Memory controller and method for copying mirrored memory that allows processor accesses to memory during a mirror copy operation A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the ... | 05/24/2011 |
| 7949638 | System and method for nearly in-band search indexing A system and method for nearly in-band search indexing. A network switch (or other intermediate network device) is configured to provide port mirroring so that data access requests directed to a storage system are forwarded to both the storage system and to a search... | 05/24/2011 |
| 7945741 | Reservation required transactions A computer readable medium is provided embodying instructions executable by a processor to perform a method for performing a transaction including a transaction head and a transaction tail, the method includes executing the transaction head, including executing at l... | 05/17/2011 |
| 7899997 | Systems and methods for implementing key-based transactional memory conflict detection Transactional memory systems and methods are provided which employ key-based transactional memory conflict detection mechanisms for enabling low-overhead conflict detection at variable granularities using customizable conflict sets that are designated using key valu... | 03/01/2011 |
| 7890706 | Delegated write for race avoidance in a processor In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate fo... | 02/15/2011 |
| 7890707 | Efficient retry for transactional memory Various technologies and techniques are disclosed for implementing retrying transactions in a transactional memory system. The system allows a transaction to execute a retry operation. The system registers for waits on every read in a read set of the retrying transa... | 02/15/2011 |
| 7870346 | Servo controller interface module for embedded disk controllers An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers... | 01/11/2011 |
| 7865671 | Efficient non-blocking K-compare-single-swap operation The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide s... | 01/04/2011 |
| 7856536 | Providing a process exclusive access to a page including a memory address to which a lock is granted to the process Provided are a method, system, and article of manufacture for providing a process exclusive access to a page including a memory address to which a lock is granted to the process. A request is received for a memory address in a memory device from a requesting process... | 12/21/2010 |
| 7844782 | Data processing system with memory access A data processing system with memory access comprising an operating system for supporting processes, such that the process are associated with one or more resources and the operating system being arranged to police the accessing by processes of resources so as to in... | 11/30/2010 |
| 7818513 | Coordinating accesses to shared objects using transactional memory mechanisms and non-transactional software mechanisms Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Softw... | 10/19/2010 |
| 7809894 | Compare, swap and store facility with no external serialization A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and ... | 10/05/2010 |
| 7793053 | Efficient non-blocking k-compare-single-swap operation The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide s... | 09/07/2010 |
| 7774557 | Storage access system and method for image forming device In one embodiment, an image forming device includes a storage device for storing data. A storage access manager is configured to coordinate access to the storage device from a plurality of client devices that communicate with the storage device using at least one un... | 08/10/2010 |
| 7765364 | Concurrent execution of critical sections by eliding ownership of locks One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without... | 07/27/2010 |
| 7752399 | Exclusion control method and information processing apparatus Disclosed is an information processing apparatus that has an update procedure semaphore, and a generation management information as management information of a shared data area that requires exclusion control. The generation management information specifies one item... | 07/06/2010 |
| 7702860 | Memory access apparatus A memory access apparatus for accessing a first memory and a second memory, includes: an address outputting unit configured to output a read address to at least one of the first and the second memories; an access request outputting unit configured to output a read r... | 04/20/2010 |
| 7689780 | Adaptive granularity refinement in detecting potential data races A method and apparatus are provided for detecting data races that overcome the limitations of the prior art. In some embodiments, this is accomplished by detecting a first access to an object, determining whether the first access is associated with a suspicious patt... | 03/30/2010 |
| 7660951 | Atomic read/write support in a multi-module memory configuration Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given r... | 02/09/2010 |
