Class 711/149 - Multiport memory

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter including means or steps for controlling
No. of patents: 544
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190828	Embedded processor with dual-port SRAM for programmable logic Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement us...	05/29/2012
8171234	Multi-bank multi-port architecture A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received o...	05/01/2012
8161249	Method and apparatus for multi-port arbitration using multiple time slots An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming...	04/17/2012
8145851	Integrated device An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, an...	03/27/2012
8127087	Memory controller for improved read port selection in a memory mirrored system Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory syst...	02/28/2012
8122199	Multi port memory device with shared memory area using latch type memory cells and driving method A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared...	02/21/2012
8090915	Packet transmission control apparatus and method A packet transmission control apparatus includes a plurality of controllers, an arbitrator, a BUSY control circuit, and a memory. The controller controls a transmission of a packet to an interface and manages a request for data to a memory and a reception of data fr...	01/03/2012
8082401	Self-timing for a multi-ported memory system Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present di...	12/20/2011
8069315	System and method for parallel scanning A system and method for parallel scanning among multiple scanning entities. According to various embodiments of the present invention, buffers are allocated from a pool of memory pages, with one packet being located on each page. Each of the pages is mapped such tha...	11/29/2011
8055854	System having memory device accessible to multiple processors A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor p...	11/08/2011
8019948	Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N num...	09/13/2011
8001334	Bank sharing and refresh in a shared multi-port memory device A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory...	08/16/2011
7984247	External memory controller node A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory ...	07/19/2011
7979646	External memory controller node A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory ...	07/12/2011
7962698	Deterministic collision detection An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving a read/write operation at a first data rate at a first port of a multi-port device, receiving a read/write...	06/14/2011
7941614	External memory controller node A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory ...	05/10/2011
7937538	External memory controller node A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory ...	05/03/2011
7937539	External memory controller node A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory ...	05/03/2011
7908440	Simultaneous personal sensing and data storage A personal sensing device that may be used for storing personal data and sensed data arbitrates and prioritizes competing requests for memory access from sensing, wireless, and wired interfaces. The personal sensing device enables power efficiency with burst-writes ...	03/15/2011
7904667	Systems and methods for monitoring and controlling binary state devices using a memory device A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by ...	03/08/2011
7840762	Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N num...	11/23/2010
7797497	System and method for providing more logical memory ports than physical memory ports Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has mult...	09/14/2010
7761668	Processor architecture having multi-ported memory A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration mod...	07/20/2010
7752398	Multi-port memory architecture for storing multi-dimensional arrays I An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional s...	07/06/2010
7747828	Systems and methods for monitoring and controlling binary state devices using a memory device A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by ...	06/29/2010
7743220	External memory controller node A computing machine and system to provide multiple independent simultaneous memory requests is disclosed. The computing machine includes a memory. A plurality of heterogeneous computational nodes embodied in an integrated circuit are configured to make requests for ...	06/22/2010
7711907	Self aligning state machine A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine...	05/04/2010
7707363	Multi-port memory architecture for storing multi-dimensional arrays II An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional s...	04/27/2010
7702859	Detachable direct memory access arrangement A new and useful DMA-like arrangement provides fast inter-system transfers of large data volumes. A preferred embodiment of the invention includes a data-transfer-out system and further includes a data-transfer-in system. At least one of the systems has a dual porte...	04/20/2010
7680988	Single interconnect providing read and write access to a memory shared by concurrent threads A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory ...	03/16/2010
7669014	Transpose memory and method thereof A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input mat...	02/23/2010
7636817	Methods and apparatus for allowing simultaneous memory accesses in a programmable chip system Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure. Memory is divided into blocks having sequential addresses based on the n...	12/22/2009
7634621	Register file allocation Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register allocation methods for storing data in a multiple-bank register file. In a t...	12/15/2009
7620780	Multiprocessor system with cache controlled scatter-gather operations Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled t...	11/17/2009
7617367	Memory system including a two-on-one link memory subsystem interconnection A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing ...	11/10/2009
7600081	Processor architecture having multi-ported memory A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N ...	10/06/2009
7596666	Multi-path accessible semiconductor memory device having port state signaling function A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared mem...	09/29/2009
7571287	Multiport memory architecture, devices and systems including the same, and methods of using the same A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of whic...	08/04/2009
7562193	Memory with single and dual mode access The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the me...	07/14/2009
7546424	Embedded processor with dual-port SRAM for programmable logic Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement us...	06/09/2009

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Class 711/149 - Multiport memory