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Thomas Watson, chairman of IBM ; 1943
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| Number | Title | Issue Date |
| 8190827 | Memory sharing among computer programs A physical memory location among multiple programs is shared among multiple programs. In one embodiment, multiple memory units are scanned to detect duplicated contents in the memory units. The memory units are used by programs running on a computer system. A data s... | 05/29/2012 |
| 8171337 | Computer architectures using shared storage Shared storage systems and methods are provided. A particular shared storage system is a system including multiple instances of shared storage. Each of the instances of shared storage includes data and file system metadata separated from the data. The file system me... | 05/01/2012 |
| 8166254 | Hypervisor page fault processing in a shared memory partition data processing system Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an ... | 04/24/2012 |
| 8024529 | Providing shared memory in a distributed computing system A distributed computing system includes a plurality of processors and shared memory service entities executable on the processors. Each of the shared memory service entities is associated with a local shared memory buffer. A producer is associated with a particular ... | 09/20/2011 |
| 7945740 | Structure for a memory switching data processing system A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’... | 05/17/2011 |
| 7941613 | Shared memory architecture Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The ran... | 05/10/2011 |
| 7937537 | Memory switching data processing system A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the mem... | 05/03/2011 |
| 7917705 | Scalable performance-based volume allocation in large storage controller collections A scalable, performance-based, volume allocation technique that can be applied in large storage controller collections is disclosed. A global resource tree of multiple nodes representing interconnected components of a storage system is analyzed to yield gap values f... | 03/29/2011 |
| 7818512 | High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in a hierarchical tree configuration, in which at least some communications from an external source traverse successive levels of the tree to reach memory modules at the lowest l... | 10/19/2010 |
| 7801903 | Shared-memory multiprocessor system and method for processing information Large-scale table data stored in a shared memory are sorted by a plurality of processors in parallel. According to the present invention, the records subjected to processing are first divided for allocation to the plurality of processors. Then, each processor counts... | 09/21/2010 |
| 7757049 | Method and system for file access using a shared memory A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first ... | 07/13/2010 |
| 7747827 | Storage system, disk control cluster, and its increase method The storage system includes disk control clusters. Each cluster has channel IF units, disk IF units and local shared memory units. The channel IF units, disk IF units and local shared memory units in the plurality of disk control clusters are connected to each other... | 06/29/2010 |
| 7739457 | Local memory management system with plural processors An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third loc... | 06/15/2010 |
| 7734878 | System and method for performing virtual device I/O operations Systems, methods, apparatus and software can make use of separated I/O processors and strategy processors (implemented in hardware and/or software) to perform virtual device I/O operations. I/O processors operating on cluster nodes, storage appliance ports, or other... | 06/08/2010 |
| 7664921 | Method for accessing shared memories and multiprocessor system using the method A method for accessing shared memory cards from each of plural processor cards is disclosed. The shared memory cards are composed of a shared memory card of an operating system and a shared memory card of a standby system in a redundant configuration, and each of pl... | 02/16/2010 |
| 7627721 | Advanced processor with cache coherency An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 12/01/2009 |
| 7539824 | Pooling and provisioning storage resources in a storage network A system in accordance with an embodiment of the invention provides Quality of Service (QoS) for Storage Access. Such QoS is partially enabled in one embodiment by the automatic pooling of storage devices and provisioning virtual targets from those pools. QoS is enf... | 05/26/2009 |
| 7536516 | Shared memory device A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory s... | 05/19/2009 |
| 7512746 | Storage system with designated CPU cores processing transactions across storage nodes A storage system comprises a plurality of storage nodes and a controller coupling unit interconnecting controllers within the storage nodes. A memory in the controller has a plurality of shared memory areas each associated with a combination of one CPU core with one... | 03/31/2009 |
| 7509462 | Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 03/24/2009 |
| 7500068 | Method and system for managing memory in a multiprocessor system A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors an... | 03/03/2009 |
| 7496717 | System for sharing storage device among controllers and method thereof The present invention discloses a system for sharing a storage device among controllers, which includes a first controller and a second controller connected with each other, and both connected to a storage device including a plurality of logical unit numbers. The co... | 02/24/2009 |
| 7484047 | Apparatus and method for composing a cache memory of a wireless terminal having a coprocessor A terminal apparatus and method for controlling access by a processor and coprocessor to data buses that connect memories. The apparatus and method comprise a first flash memory connected to a second data bus and having a first area for storing operation programs of... | 01/27/2009 |
| 7437534 | Local and global register partitioning technique A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the pluralit... | 10/14/2008 |
| 7434006 | Non-speculative distributed conflict resolution for a cache coherency protocol A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward... | 10/07/2008 |
| 7424579 | Memory controller for processor having multiple multithreaded programmable units A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control ... | 09/09/2008 |
| 7406574 | Management of invalid tracks A method for implementing the invention is carried out in a data-storage system having a data storage unit that includes at least two constituent data storage elements. Each of the constituent data storage elements is either in a first state or a second state. The m... | 07/29/2008 |
| 7404048 | Inter-cluster communication module using the memory access network An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an ... | 07/22/2008 |
| 7404044 | System and method for data transfer between multiple processors A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency ... | 07/22/2008 |
| 7395379 | Methods and apparatus for responding to a request cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluste... | 07/01/2008 |
| 7395381 | Method and an apparatus to reduce network utilization in a multiprocessor system A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion ... | 07/01/2008 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associat... | 06/17/2008 |
| 7389387 | Distributed memory module cache writeback One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 06/17/2008 |
| 7386596 | High performance storage access environment The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can prov... | 06/10/2008 |
| 7386598 | Computer system with virtualization function A method of creating a copy of a virtualized storage region in a data processing system for virtualizing the storage region. A server manages the correlation between the virtualized storage region and the physical storage region, utilizes the function of the storage... | 06/10/2008 |
| 7383396 | Method and apparatus for monitoring processes in a non-uniform memory access (NUMA) computer system A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different nodes. The monitoring process intelligently collects data from monit... | 06/03/2008 |
| 7383361 | Disk array system and interface converter The present invention aims to provide a high-reliability, low-cost disk array by emulating an ATA drive so that it can be used in the same way as an FC drive. To achieve this object, a disk array system of the present invention includes: a storage device having a lo... | 06/03/2008 |
| 7383336 | Distributed shared resource management A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethor... | 06/03/2008 |
| 7376800 | Speculative multiaddress atomicity A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the sha... | 05/20/2008 |
| 7376790 | Caching media data using content sensitive object identifiers Techniques for caching media data, including streaming media data, using content-sensitive identifiers. The content-sensitive identifiers enable a caching proxy or a caching server to unambiguously determine the version or contents of media data cached by the cachin... | 05/20/2008 |
