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| Number | Title | Issue Date |
| 8117156 | Replication for common availability substrate Systems and methods that supply a replication layer/agent that is generic to supporting a plurality of storage configuration as part of a distributed store. Such distributed store employs a Common Availability Substrate (CAS) for data transport and consistency, to r... | 02/14/2012 |
| 8108623 | Poll based cache event notifications in a distributed cache Systems and methods that supply poll based notification system in a distributed cache, for tracking changes to cache items. Local caches on the client can employ the notification system to keep the local objects in sync with the backend cache service; and can furthe... | 01/31/2012 |
| 8108624 | Data cache with modified bit array A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined orga... | 01/31/2012 |
| 8099559 | System and method for generating fast instruction and data interrupts for processor design verification and validation A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation e... | 01/17/2012 |
| 8078807 | Accelerating software lookups by using buffered or ephemeral stores A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value.... | 12/13/2011 |
| 7991965 | Technique for using memory attributes A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner. ... | 08/02/2011 |
| 7949834 | Method and apparatus for setting cache policies in a processor According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor compri... | 05/24/2011 |
| 7941610 | Coherency directory updating in a multiprocessor computing system Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache inclu... | 05/10/2011 |
| 7886114 | Storage controller for cache slot management When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel process... | 02/08/2011 |
| 7873793 | Supporting speculative modification in a data cache Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality ... | 01/18/2011 |
| 7873794 | Mechanism that provides efficient multi-word load atomicity Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidit... | 01/18/2011 |
| 7831776 | Dynamic allocation of home coherency engine tracker resources in link based computing system A home agent allocates trackers to each of a plurality of caching agents, monitors each caching agent's usage of the allocated trackers, and determines whether a caching agent under-utilizes or over-utilizes them. In the case of under-utilization, the home agent ret... | 11/09/2010 |
| 7809893 | Method and apparatus for refetching data Methods and apparatus for refetching data to store in a cache are disclosed. According to one aspect of the present invention, a method includes identifying a speculative set that identifies at least a first element that is associated with a cache. The first element... | 10/05/2010 |
| 7788453 | Redirection of storage access requests based on determining whether write caching is enabled Provided are a method, system, and article of manufacture, wherein a controller receives a request from one of a plurality of hosts. The controller determines whether a primary storage control unit coupled to the controller is operational. A response is generated by... | 08/31/2010 |
| 7783841 | Efficient coherency communication utilizing an IG coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a me... | 08/24/2010 |
| 7783840 | Method and apparatus for controlling memory system A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure s... | 08/24/2010 |
| 7774555 | Data processing system and method for efficient coherency communication utilizing coherency domain indicators In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the firs... | 08/10/2010 |
| 7765362 | Efficient system bootstrap loading An efficient system for bootstrap loading scans cache lines into a cache store queue during a scan phase, and then transmits the cache lines from the cache store queue to a cache memory array during a functional phase. Scan circuitry stores a given cache line in a s... | 07/27/2010 |
| 7757047 | Missing store operation accelerator Maintaining a cache of indications of exclusively-owned coherence state for memory space units (e.g., cache line) allows reduction, if not elimination, of delay from missing store operations. In addition, the indications are maintained without corresponding data of ... | 07/13/2010 |
| 7747826 | Data processing system and method for efficient communication utilizing an in coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memor... | 06/29/2010 |
| 7725661 | Data-aware cache state machine Management of a Cache is provided by differentiating data base on attributes associated with the data and reducing storage bottlenecks. The Cache differentiates and manages data using a state machine with a plurality of states. The Cache may use data patterns and st... | 05/25/2010 |
| 7676637 | Location-aware cache-to-cache transfers In shared-memory multiprocessor systems, cache interventions from different sourcing caches can result in different cache intervention costs. With location-aware cache coherence, when a cache receives a data request, the cache can determine whether sourcing the data... | 03/09/2010 |
| 7620778 | Low power microprocessor cache memory and method of operation Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memor... | 11/17/2009 |
| 7620779 | System and method for handling direct memory accesses Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known ... | 11/17/2009 |
| 7613884 | Multiprocessor system and method ensuring coherency between a main memory and a cache memory A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a copy of a part of a memory region group of the main memory of one node. ... | 11/03/2009 |
| 7606980 | Demand-based error correction A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performanc... | 10/20/2009 |
| 7584329 | Data processing system and method for efficient communication utilizing an Ig coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a me... | 09/01/2009 |
| 7581067 | Load when reservation lost instruction for performing cacheline polling A load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process the... | 08/25/2009 |
| 7558923 | Prevention of live-lock in a multi-processor system Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to... | 07/07/2009 |
| 7555611 | Memory management of local variables upon a change of context A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory pref... | 06/30/2009 |
| 7523267 | Method for ensuring fairness among requests within a multi-node computer system A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed... | 04/21/2009 |
| 7509461 | Method and apparatus for intelligent buffer cache pre-emption The present invention augments each entry in a memory frame table to include information associated with the availability of any page that is buffer cache allocated. The availability information may include, for example, a link to a buffer cache descriptor associate... | 03/24/2009 |
| 7502894 | Shared rowset Multiple Shared Rowsets, can access rows of data stored in a Cached Rowset independently. These Shared Rowsets can have their own cursor, sorted order, filtered rows, and pending changes. ... | 03/10/2009 |
| 7496715 | Programmable cache management system and method A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control i... | 02/24/2009 |
| 7493453 | System, method and storage medium for prefetching via memory block tags A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag i... | 02/17/2009 |
| 7487299 | Cache memory to support a processor's power mode of operation A system, method, and apparatus for a cache memory to support a low power mode of operation. ... | 02/03/2009 |
| 7484044 | Method and apparatus for joint cache coherency states in multi-interface caches A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for... | 01/27/2009 |
| 7480772 | Data processing system and method for efficient communication utilizing an Tn and Ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a r... | 01/20/2009 |
| 7478203 | Technique for eliminating dead stores in a processor A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the... | 01/13/2009 |
| 7475196 | Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache mem... | 01/06/2009 |
