Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 8112589 | System for caching data from a main memory with a plurality of cache states To ensure efficient access to a memory whose writing process is slow. There is provided a storage device for caching data read from a main memory and data to be written in the main memory, comprises a cache memory having a plurality of cache segments, one or more ca... | 02/07/2012 |
| 8055849 | Reducing cache pollution of a software controlled cache Reducing cache pollution of a software controlled cache is provided. A request is received to prefetch data into the software controlled cache. A first designator is set for a first cache access to a first value. If there is the second cache access to prefetch, a de... | 11/08/2011 |
| 7987320 | Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the ba... | 07/26/2011 |
| 7971001 | Least recently used eviction implementation Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction ... | 06/28/2011 |
| 7962695 | Method and system for integrating SRAM and DRAM architecture in set associative cache A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining... | 06/14/2011 |
| 7917700 | Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a require... | 03/29/2011 |
| 7861041 | Second chance replacement mechanism for a highly associative cache memory of a processor A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corres... | 12/28/2010 |
| 7802057 | Priority aware selective cache allocation A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation pr... | 09/21/2010 |
| 7711904 | System, method and computer program product for executing a cache replacement algorithm A system, method and computer program product for executing a cache replacement algorithm. A system includes a computer processor having an instruction processor, a cache and one or more useful indicators. The instruction processor processes instructions in a runnin... | 05/04/2010 |
| 7711905 | Method and system for using upper cache history information to improve lower cache data replacement A system for managing data in a plurality of storage locations. In response to a least recently used algorithm wanting to move data from a cache to a storage location, an aging table is searched for an associated entry for the data. In response to finding the associ... | 05/04/2010 |
| 7640399 | Mostly exclusive shared cache management policies A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candid... | 12/29/2009 |
| 7627719 | Cache device and method for determining LRU identifier by pointer values The invention provides a cache device and method for performing a cache process on a cache memory having a high capacity in a high speed. The cache processing section performs a cache process composed of two-stage processes, a query process (P1) and a subsequ... | 12/01/2009 |
| 7512739 | Updating a node-based cache LRU tree Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low ... | 03/31/2009 |
| 7437513 | Cache memory with the number of operated ways being changed according to access pattern An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a c... | 10/14/2008 |
| 7437516 | Programming models for eviction policies Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction ... | 10/14/2008 |
| 7434247 | System and method for determining the desirability of video programming events using keyword matching The desirability of programming events may be determined using metadata for programming events that includes goodness of fit scores associated with categories of a classification hierarchy one or more of descriptive data and keyword data. The programming events are ... | 10/07/2008 |
| 7406568 | Buffer allocation for split data messages A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of dat... | 07/29/2008 |
| 7406512 | Automatic migration of data via a distributed computer network A method and apparatus for the automatic migration of data via a distributed computer network allows a customer to select content files that are to be transferred to a group of edge servers. Origin sites store all of a customer's available content files. An edge ser... | 07/29/2008 |
| 7401189 | Pipelining D states for MRU steerage during MRU/LRU member allocation A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A l... | 07/15/2008 |
| 7398357 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a ca... | 07/08/2008 |
| 7395373 | Set-associative cache using cache line decay counts and set overflow Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss occurs within the primary set, a cache line from the primary set is select... | 07/01/2008 |
| 7386673 | Method for tracking of non-resident pages Embodiments of the present invention provide methods and systems for efficiently tracking evicted or non-resident pages. For each non-resident page, a first hash value is generated from the page's metadata, such as the page's mapping and offset parameters. This firs... | 06/10/2008 |
| 7380047 | Apparatus and method for filtering unused sub-blocks in cache memories A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered po... | 05/27/2008 |
| 7373404 | Suspension and reinstatement of reference A handle administration system is described in which software agents receive handles to various resources that they can use to obtain the resources. The described embodiments provide multiple states that can be assumed by the handles. An unassigned state is provided... | 05/13/2008 |
| 7373480 | Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a secon... | 05/13/2008 |
| 7370222 | External storage and data recovery method for external storage as well as program The data is automatically recovered to a desired arbitrary point in an external storage without imposing a burden on the host computer. An application on a host computer instructs data recovery control processing of a disk control apparatus to set a recovery opportu... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366871 | Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each addre... | 04/29/2008 |
| 7363433 | Cache member protection with partial make MRU allocation A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of ... | 04/22/2008 |
| 7363430 | Determination of cache entry for future operation A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K ... | 04/22/2008 |
| 7360043 | Method and apparatus for efficiently determining rank in an LRU list One embodiment of the present invention provides a system that manages an LRU list such that the rank, or position, of data records in the sequence can be determined efficiently. The system initializes an index field in each record to the record's initial rank. When... | 04/15/2008 |
| 7360042 | Determining when to evict unused items from storage Items that are in use are maintained in a used item store. Items that are no longer in use are placed in an unused items store. When an item that is not currently in use is requested again, an attempt is made to retrieve the item from the unused item store. Retrievi... | 04/15/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7356651 | Data-aware cache state machine A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the bottleneck to storage. The data-aware cache differentiates and manages dat... | 04/08/2008 |
| 7356641 | Data management in flash memory A method is disclosed for emulating a disk drive on flash memory, thus enabling one or more file-systems to be resident on flash memory. A list of data structures is maintained corresponding to certain sectors resident on flash memory. Certain characteristics of dat... | 04/08/2008 |
| 7356650 | Cache apparatus and method for accesses lacking locality Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a ... | 04/08/2008 |
| 7353146 | Block processing of input data in graphical programming environments Methods and systems for performing block processing of input data in graphical programming environments are disclosed. The input data that is to be processed is partitioned into a plurality of blocks. Each block of the input data is applied to the data processing un... | 04/01/2008 |
| 7353241 | Method, medium and system for recovering data using a timeline-based computing environment The present description discloses a technique for recovering data using a timeline-based computing environment. Data items of the application are periodically saved for recovery such that the saved data items can be used to recover the application at a point in time... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7353337 | Reducing cache effects of certain code pieces Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution ... | 04/01/2008 |
