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| Number | Title | Issue Date |
| 8180967 | Transactional memory virtualization Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transac... | 05/15/2012 |
| 8180968 | Reduction of cache flush time using a dirty line limiter The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populat... | 05/15/2012 |
| 8024525 | Storage control unit with memory cache protection via recorded log A “Logging” method and apparatus is provided to protect control unit cached data not yet written to backing storage disk drives. This recording mechanism copies “WRITE DATA” to a log at a target logically external or physically external to storage control un... | 09/20/2011 |
| 7966456 | Method for reducing number of writes in a cache memory Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a se... | 06/21/2011 |
| 7958312 | Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in ... | 06/07/2011 |
| 7937531 | Regularly occurring write back scheme for cache soft error reduction In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries a... | 05/03/2011 |
| 7904659 | Power conservation via DRAM access reduction Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA dev... | 03/08/2011 |
| 7899995 | Apparatus, system, and method for dependent computations of streaming multiprocessors An array of streaming multiprocessors shares data via a shared memory. A flushing mechanism is used to guarantee that data required for dependent computations is available in the shared memory. ... | 03/01/2011 |
| 7873790 | Mass storage system and method with emulation and management priorities The present invention concerns a storage method and system (1) comprising processing means (11) and storage resources (20, 100) containing firstly storage means (20) including at least one physical library (P201 to P2... | 01/18/2011 |
| 7827358 | Memory management methods and systems A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) in... | 11/02/2010 |
| 7779207 | Accelerated write performance A generic disk driver filter may be used to accelerate performance when writing to a disk. The generic disk driver filter may be connected between a file system and a disk driver and may be configured to be extensible and compatible with a variety of different file ... | 08/17/2010 |
| 7765361 | Enforced transaction system recoverability on media without write-through To ensure that logs representative of data changes are durably written, localized storage media cache is flushed to force a write to stable storage. Log sequence number tracking is leveraged to determine if log data in a localized storage media cache is likely to ha... | 07/27/2010 |
| 7752173 | Method and apparatus for improving data processing system performance by reducing wasted disk writes Data with a short useful lifetime are received and cached by a system. The system waits for the first to occur of two events. If the first event is a local cache flush trigger, the data is written to a longer-term storage subsystem. If the first event is a remote ca... | 07/06/2010 |
| 7721049 | Disk drive write method A disk drive includes a first flush cache memory location, a second flush cache memory location, and a controller for writing information associated with a flush cache write command alternatively between the first flush cache memory location and the second flush cac... | 05/18/2010 |
| 7685371 | Hierarchical flush barrier mechanism with deadlock avoidance A data processing system can establish or maintain data coherency by issuing a data flush operation. The data processing system can be configured as a host executing one or more independent processes using one or more lower level devices. The lower level devices can... | 03/23/2010 |
| 7685370 | Data synchronization with multiple producers A data processing system can establish or maintain data coherency by issuing a data flush operation. An agent can initialize a first flush operation by writing to a flush register. The agent can determine that the flush operation is complete by reading a status indi... | 03/23/2010 |
| 7676634 | Selective trace cache invalidation for self-modifying code via memory aging Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enab... | 03/09/2010 |
| 7631147 | Efficient flushing of translation lookaside buffers in a multiprocessor environment Various operations are disclosed for improving the operational efficiency of address mapping caches, such as translation lookaside buffers, in a multiprocessor environment. When an address mapping translation is invalidated, unnecessary address mapping cache flushes... | 12/08/2009 |
| 7617363 | Low latency message passing mechanism In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM (“direct messaging”) packet to a memory from a first cache line associated with a first processor; obtaining... | 11/10/2009 |
| 7574565 | Transforming flush queue command to memory barrier command in disk drive In a HDD, the flush queue (cache) command is transformed into a memory barrier command. The HDD thus has an operation mode in which flush commands do not cause the pending commands to be executed immediately, but instead simply introduces a constraint on the command... | 08/11/2009 |
| 7539822 | Method and apparatus for facilitating faster execution of code on a memory-constrained computing device One embodiment of the present invention provides a system that facilitates faster execution of code on a memory-constrained computing device that has fast on-chip RAM, wherein the fast on-chip RAM is located on a processor chip, but is not cache memory. The system o... | 05/26/2009 |
| 7523264 | Apparatus, system, and method for dependent computations of streaming multiprocessors An array of streaming multiprocessors shares data via a shared memory. A flushing mechanism is used to guarantee that data required for dependent computations is available in the shared memory. ... | 04/21/2009 |
| 7461210 | Managing set associative cache memory according to entry type Managing memory includes: mediating access to a first memory as a cache for a second memory; and associating one of a plurality of entry types with entries in the cache. Data from the second memory associated with a first type is not allowed to evict a cache entry a... | 12/02/2008 |
| 7457921 | Write barrier for data storage integrity A system that facilitates the storage of data using a write barrier. The system interfaces to a hardware component that stores data, and includes a write barrier component that dynamically employs instructions compatible with the hardware component to ensure data in... | 11/25/2008 |
| 7451275 | Programming models for storage plug-ins Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the regi... | 11/11/2008 |
| 7444478 | Priority scheme for transmitting blocks of data Provided are techniques for transmitting blocks of data. It is determined whether any high priority out of sync (HPOOS) indicator is set to indicate that a number of modified segments associated with a block of data are less than or equal to a modified segments thre... | 10/28/2008 |
| 7437516 | Programming models for eviction policies Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction ... | 10/14/2008 |
| 7434247 | System and method for determining the desirability of video programming events using keyword matching The desirability of programming events may be determined using metadata for programming events that includes goodness of fit scores associated with categories of a classification hierarchy one or more of descriptive data and keyword data. The programming events are ... | 10/07/2008 |
| 7434003 | Efficient operating system operation on a hypervisor An operating system is described that is capable of ascertaining whether it is executing in a virtual machine environment and is further capable of modifying its behavior to operate more efficiently and provide optimal behavior in a virtual machine environment. An o... | 10/07/2008 |
| 7430638 | Adaptive input / output compressed system and data cache and system using same To improve caching techniques, so as to realize greater hit rates within available memory, of the present invention utilizes a entropy signature from the compressed data blocks to supply a bias to pre-fetching operations. The method of the present invention for cach... | 09/30/2008 |
| 7428616 | Method and apparatus for appending buffer areas to requested memory An information processing apparatus has a CPU, a memory, a cache memory and a cache controller. When an acquisition of an area of a prescribed size is requested in the memory, a size equivalent to at least two lines serving as a cache unit is added to the prescribed... | 09/23/2008 |
| 7421535 | Method for demoting tracks from cache Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged track... | 09/02/2008 |
| 7418547 | System and method to protect data stored in a storage system In an example of an embodiment of the invention, a method is provided for recording data transmitted to a storage system, wherein the storage system has a cache and at least one storage device, and the data comprises initial data items that are transmitted to the st... | 08/26/2008 |
| 7412466 | Offset-based forward address calculation in a sliding-compaction garbage collector When calculating post-compaction destination addresses during sliding heap compaction, a block of contiguous memory objects may be treated as a single unit by adding the offset of each object in the block to the post-compaction address for the first object in the bl... | 08/12/2008 |
| 7401190 | Software management Methods and systems for operating computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which critical data, e... | 07/15/2008 |
| 7398357 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a ca... | 07/08/2008 |
| 7395381 | Method and an apparatus to reduce network utilization in a multiprocessor system A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion ... | 07/01/2008 |
| 7389387 | Distributed memory module cache writeback One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data c... | 06/17/2008 |
| 7386669 | System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache m... | 06/10/2008 |
| 7383168 | Method and system for design verification and debugging of a complex computing system A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based... | 06/03/2008 |
