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| Number | Title | Issue Date |
| 7934057 | Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs Embodiments of the invention are directed to systems and method for providing predictable timing for read operations in a multiport memory device. Accordingly, an embodiment is directed to a multiport memory system, comprising a single port memory core synchronized ... | 04/26/2011 |
| 7818504 | Storage system that prioritizes storage requests A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interle... | 10/19/2010 |
| 7694077 | Multi-port integrated cache A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction p... | 04/06/2010 |
| 7526612 | Multiport cache memory which reduces probability of bank contention and access control system thereof A multiport cache memory is provided which enables reduction of a probability of bank contention which will occur when a plurality of read operations are executed simultaneously, and an access control system of the multiport cache memory. ... | 04/28/2009 |
| 7467261 | Dual storage apparatus and control method for the dual storage apparatus A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a... | 12/16/2008 |
| 7421559 | Apparatus and method for a synchronous multi-port memory A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also inc... | 09/02/2008 |
| 7401186 | System and method for tracking changes in L1 data cache directory Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old... | 07/15/2008 |
| 7373453 | Method and apparatus of interleaving memory bank in multi-layer bus system A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals gene... | 05/13/2008 |
| 7373478 | Information processing apparatus and software pre-fetch control method In an information processing apparatus (10) that includes a cache memory (560) formed from at least one hierarchy, and a pre-fetch command that speculatively transfers data or a command from a main storage (30) to the cache memory, a cache contr... | 05/13/2008 |
| 7366931 | Memory modules that receive clock information and are placed in a low power state Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to ... | 04/29/2008 |
| 7366821 | High-speed memory system A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing ... | 04/29/2008 |
| 7363450 | Method and apparatus for estimating multithreaded processor throughput based on processor cache performance An estimate is calculated of the throughput of a multi-threaded processor having N threads based on measured miss rates of a cache memory associated with the processor by calculating, based on the cache miss rates a probability that the processor is in a state with ... | 04/22/2008 |
| 7363430 | Determination of cache entry for future operation A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K ... | 04/22/2008 |
| 7360024 | Multi-port integrated cache A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction p... | 04/15/2008 |
| 7359275 | Reduced size dual-port SRAM cell A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further includes read access circuitry dedicated exclusively to a read operation ... | 04/15/2008 |
| 7356639 | Configurable width buffered module having a bypass circuit A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or ... | 04/08/2008 |
| 7353316 | System and method for re-routing signals between memory system components A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub c... | 04/01/2008 |
| 7346739 | First-in-first-out memory system and method for providing same First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of FIFOs, second storage locations for storing status information for each of... | 03/18/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7340562 | Cache for instruction set architecture A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number... | 03/04/2008 |
| 7340568 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 03/04/2008 |
| 7337372 | Method and apparatus for detecting multi-hit errors in a cache Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If mult... | 02/26/2008 |
| 7320053 | Banking render cache for multiple access A cache memory system may be is organized as a set of numbered banks. If two clients need to access the cache, a contention situation may be resolved by a contention resolution process. The contention resolution process may be based on relative priorities of the cli... | 01/15/2008 |
| 7318122 | Disk array control device with an internal connection system for efficient data transfer A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an i... | 01/08/2008 |
| 7310706 | Random cache line refill A microprocessor includes random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the o... | 12/18/2007 |
| 7307912 | Variable data width memory systems and methods Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique for doubling a width of a memory is disclosed, without having to increase a width of the internal data pa... | 12/11/2007 |
| 7296166 | Disk array system for starting destaging process of unwritten cache memory data to disk drive upon detecting DC voltage level falling below predetermined value A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the channel control portion, the disk control portion, the cache memory, th... | 11/13/2007 |
| 7293141 | Cache word of interest latency organization Techniques for improving cache latency include distributing cache lines across regions of the cache having various latencies. The latencies of the regions may vary as a function of the distance between an individual region of the cache and a cache controller. The ca... | 11/06/2007 |
| 7280386 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/09/2007 |
| 7278008 | Virtual address translation system with caching of variable-range translation clusters A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 10/02/2007 |
| 7277345 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/02/2007 |
| 7275200 | Transparent error correcting memory that supports partial-word write A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are e... | 09/25/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7266663 | Automatic cache activation and deactivation for power reduction The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is mea... | 09/04/2007 |
| 7254677 | First-in, first-out memory system with reduced cycle latency A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the out... | 08/07/2007 |
| 7249245 | Globally observing load operations prior to fence instruction and post-serialization modes A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first in... | 07/24/2007 |
| 7234022 | Cache accumulator memory for performing operations on block operands Various embodiments of systems and methods for performing accumulation operations on block operands are disclosed. In one embodiment, an apparatus may include a memory, a functional unit that performs an operation on block operands, and a cache accumulator. The cach... | 06/19/2007 |
| 7225290 | ATA and SATA compliant controller An ATA (Advanced Technology Attachment) controller is provided that comprises at least one parallel port for connecting to at least one ATA compliant storage device, and at least one serial port for connecting to at least one SATA (Serial ATA) compliant storage devi... | 05/29/2007 |
| 7225308 | Inexpensive reliable computer storage via hetero-geneous architecture and a staged storage policy An inexpensive storage system is disclosed along with methods of managing such a system. In one preferred embodiment, the system includes a high performance high reliability storage medium configured for initial storage of data, a low performance high reliability st... | 05/29/2007 |
| 7222169 | Control method and system for information delivery through mobile communications network A control method and system for information delivery in a mobile communications network in which, as a mobile terminal moves from a communication area to another, a cache node in a delivery channel which delivers cache information to the mobile terminal is switched ... | 05/22/2007 |
