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| Number | Title | Issue Date |
| 8364896 | Method and apparatus for configuring a unified cache based on an associated error rate A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is selected based at least in part on the associated error rate. The unified ... | 01/29/2013 |
| 8171225 | Cache for a multi thread and multi core system and methods thereof A method includes storing a plurality of data RAM, holding information for all outstanding requests forwarded to a next-level memory subsystem, clearing information associated with a serviced request after the request has been fulfilled, determining if a subsequent ... | 05/01/2012 |
| 8140761 | Event tracking hardware An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The event tracking engine stores a cumulative number of occurrences for each one of the different kinds of events, and searches in the N ... | 03/20/2012 |
| 7707358 | Dual access for single port cache A method and system for accessing a single port multi-way cache with way dedication includes address multiplexers that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively sel... | 04/27/2010 |
| 7634619 | Method and apparatus for redirection of operations between interfaces A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages to both the instruction memory and the data memory. An instruction memory interface... | 12/15/2009 |
| 7552283 | Efficient memory hierarchy management In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an in... | 06/23/2009 |
| 7406569 | Instruction cache way prediction for jump targets Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way predictio... | 07/29/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7395380 | Selective snooping by snoop masters to locate updated data A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originat... | 07/01/2008 |
| 7388876 | Method and system for transmitting data in two steps by using data storage provided in data transmission equipment in network In a method for transmitting data from a first node to a second node through an interlinking network including data transmission equipments: the data is transmitted from the first node to one of the data transmission equipments together with a first request for stor... | 06/17/2008 |
| 7370123 | Information processing apparatus A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A ... | 05/06/2008 |
| 7363391 | Storage system for queuing I/O commands and control method therefor A conventional storage system immediately executes a received I/O command because of importance of response time. Provided is a storage system which is coupled to a network and executes an I/O command received from at least one host computer through the network, in ... | 04/22/2008 |
| 7360028 | Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The instruction is received and executed. After the instruction space is... | 04/15/2008 |
| 7360022 | Synchronizing an instruction cache and a data cache on demand In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instr... | 04/15/2008 |
| 7360024 | Multi-port integrated cache A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction p... | 04/15/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7336623 | Peer-to-peer cloud-split detection and repair methods A method for detecting and repairing cloud splits in a distributed system such as a peer-to-peer (P2P) system is presented. Nodes in a cloud maintain a multilevel cache of entries for a subset of nodes in the cloud. The multilevel cache is built on a circular number... | 02/26/2008 |
| 7334086 | Advanced processor with system on a chip interconnect technology An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 02/19/2008 |
| 7330954 | Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the storage parameter indicates use of the information by a software proce... | 02/12/2008 |
| 7328433 | Methods and apparatus for reducing memory latency in a software application Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A perfo... | 02/05/2008 |
| 7310709 | Method and apparatus for primary cache tag error handling A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary ... | 12/18/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7251710 | Cache memory subsystem including a fixed latency R/W pipeline A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be conf... | 07/31/2007 |
| 7249352 | Apparatus and method for removing elements from a linked list Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one embodiment, the method, apparatus and computer program product include... | 07/24/2007 |
| 7228410 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 06/05/2007 |
| 7228385 | Processor, data processing system and method for synchronizing access to data in shared memory A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to... | 06/05/2007 |
| 7227589 | Method and apparatus for video decoding on a multiprocessor system A method and apparatus for decoding compressed video. The method includes reading a stream of compressed video into a memory. The video includes multiple pictures, with each picture having one or more independent elements. Thereafter, assigning, via a first processo... | 06/05/2007 |
| 7228409 | Networking interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 06/05/2007 |
| 7203798 | Data memory cache unit and data memory cache system A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit 117 executes reading and writing of data in a 16-byte width line unit in a main memory unit 131, executes reading and writing of data in an ... | 04/10/2007 |
| 7194605 | Cache for instruction set architecture using indexes to achieve compression A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions be... | 03/20/2007 |
| 7178018 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/13/2007 |
| 7178017 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/13/2007 |
| 7177986 | Direct access mode for a cache A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons a... | 02/13/2007 |
| 7174449 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/06/2007 |
| 7174448 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/06/2007 |
| 7174450 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 02/06/2007 |
| 7167978 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 01/23/2007 |
| 7167977 | Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode logic, and kernel mode to user mode interface logic. The interface l... | 01/23/2007 |
| 7142541 | Determining routing information for an information packet in accordance with a destination address and a device address According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address. ... | 11/28/2006 |
| 7133968 | Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stall... | 11/07/2006 |
