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| Number | Title | Issue Date |
| 8117391 | Storage system and data management method A storage system, which is coupled to a computer, includes a storage device, a controller, a plurality of cache memory units, and a connecting unit. Each of the plurality of cache memory units includes: a cache memory for storing data; an auxiliary storage device fo... | 02/14/2012 |
| 8095733 | Virtual barrier synchronization cache castout election A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processi... | 01/10/2012 |
| 8082465 | Auto-adapting cache memory system and method A system, method and computer program product for detecting a failed storage device within an “n” device array. The “n” device array is configured to store “n” device array formatted data. The “n” device array is reconfigured into an “n−1” devi... | 12/20/2011 |
| 8046538 | Method and mechanism for cache compaction and bandwidth reduction A method and mechanism are managing caches. A cache is configured to store blocks of data based upon predictions of future accesses. Each block is partitioned into sub-blocks, and if it is predicted a given sub-block is unlikely to be accessed, the sub-block may not... | 10/25/2011 |
| 7996615 | Cache region concept A method to associate a storage policy with a cache region is disclosed. In this method, a cache region associated with an application is created. The application runs on virtual machines, and where a first virtual machine has a local memory cache that is private to... | 08/09/2011 |
| 7958308 | Recording controller and recording control method Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with resp... | 06/07/2011 |
| 7941603 | Method and apparatus for implementing cache coherency of a processor An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 05/10/2011 |
| 7904657 | Cache residence prediction The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memor... | 03/08/2011 |
| 7882307 | Managing cache memory in a parallel processing environment An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for... | 02/01/2011 |
| 7870339 | Extract cache attribute facility and instruction therefore A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) ... | 01/11/2011 |
| 7865667 | Multi-core multi-thread processor In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodi... | 01/04/2011 |
| 7856530 | System and method for implementing a dynamic cache for a data storage system A dynamic cache system is configured to flexibly respond to changes in operating parameters of a data storage and retrieval system. A cache controller in the system implements a caching policy describing how and what data should be cached. The policy can provide dif... | 12/21/2010 |
| 7831772 | System and methodology providing multiple heterogeneous buffer caches A method for temporarily storing data objects in memory of a distributed system comprising a plurality of servers sharing access to data comprises steps of: reserving memory at each of the plurality of servers as a default data cache for storing data objects; in res... | 11/09/2010 |
| 7827353 | Self healing memory A method for managing a data storage system, consisting of configuring a first cache to retrieve data from and store data at a first range of logical addresses (LAs) in a storage device. A second cache is configured to operate like the first cache. The method furthe... | 11/02/2010 |
| 7779205 | Coherent caching of local memory data A multi processor system 1 comprises a plurality of processors 21 to 25, a system bus 30 and a main system memory 40. Each processor 21 to 25 is connected to a respective cache memory 41 to 45, with each... | 08/17/2010 |
| 7761664 | Systems and methods for multi-level exclusive caching using hints Systems and methods for multi-level exclusive caching using hints. Exemplary embodiments include a method for multi-level exclusive caching, the method including identifying a cache management protocol within a multi-level cache hierarchy having a plurality of cache... | 07/20/2010 |
| 7761663 | Operating a replicated cache that includes receiving confirmation that a flush operation was initiated A unit of data is read from memory of a replicated cache. The replicated cache comprises a plurality of independent computing devices. Each independent computing device comprises a processor and a portion of the memory. Confirmations are received from at least a maj... | 07/20/2010 |
| 7725655 | Method of operating distributed storage system in which data is read from replicated caches and stored as erasure-coded data Data blocks are read from a distributed cache. The distributed cache comprises m replicated caches, each replicated cache including a plurality of independent computing devices. Each independent computing device of the replicated caches holds a replica of a particul... | 05/25/2010 |
| 7711899 | Information processing device and data control method in information processing device An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temp... | 05/04/2010 |
| 7694075 | System for enabling and disabling cache and a method thereof A second cache (e.g., L2 cache) is enabled or disabled based at least in part on an utilization of a first cache (e.g., L1 cache). The utilization of the first cache may be interpreted as an estimation of the likely utilization of the second cache. The utilization m... | 04/06/2010 |
| 7673100 | Methods and systems for distributed cache tag management Methods and systems are disclosed that relate to locating cached data corresponding to data in persistent memory within a data storage facility. An exemplary method includes receiving a request for data in persistent memory, applying a function to a persistent memor... | 03/02/2010 |
| 7627717 | Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 12/01/2009 |
| 7562190 | Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability of proximity interconnect, enhancements to the cache protocol to impro... | 07/14/2009 |
| 7552282 | Method, computer readable medium, and data storage system for selective data replication of cached data Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is ... | 06/23/2009 |
| 7549021 | Enhanced data integrity using parallel volatile and non-volatile transfer buffers Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block... | 06/16/2009 |
| 7519774 | Data processor having a memory control unit with cache memory The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable... | 04/14/2009 |
| 7509457 | Non-homogeneous multi-processor system with shared memory A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a contro... | 03/24/2009 |
| 7496712 | Proximity communication-based off-chip cache memory architectures A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a plurality of processors that are dependent on the plurality of off-chip cache... | 02/24/2009 |
| 7472224 | Reconfigurable processing node including first and second processor cores In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache ... | 12/30/2008 |
| 7451274 | Memory control device, move-in buffer control method A central processor executes at least a load command, a store command, and a prefetch command based on an out-of-order processing for processing commands by changing the order of executing the commands. A valid move-in buffer (MIB) detector detects the number of pri... | 11/11/2008 |
| 7447842 | Mass memory device and method for operating a mass memory device A mass memory device (1) having a plurality of mass memories (2) and having at least two bridge controllers (3) which are coupled to the mass memories (2) by a data bus. A first common cache memory unit (4) is provided, to which th... | 11/04/2008 |
| 7444473 | Speculative memory accesses in a proximity communication-based off-chip cache memory architecture A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability of proximity interconnect, when an off-chip cache memory is searched f... | 10/28/2008 |
| 7437520 | Adaptive snoop-and-forward mechanisms for multiprocessor systems In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be... | 10/14/2008 |
| 7426611 | Method and system for improved storage system performance using cloning of cached data A method for improving storage system performance is disclosed. The method includes cloning information stored in a first unit of storage in a second unit of storage. The first unit of storage is stored in a first cache maintained by an upper-level system, while the... | 09/16/2008 |
| 7421538 | Storage control apparatus and control method thereof A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and high-speed operation is enabled. The mirror management table is created w... | 09/02/2008 |
| 7421541 | Version management of cached permissions metadata Techniques are provided for performing transaction-aware caching of metadata in an electronic file system. A mechanism is described for providing transaction-aware caching that uses a cache hierarchy, where the cache hierarchy includes uncommitted caches associated ... | 09/02/2008 |
| 7418559 | Address snoop method and multi-processor system Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the upper limit of the performance of the multi-processor system from det... | 08/26/2008 |
| 7418558 | Information processing system, system control apparatus, and system control method A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received extern... | 08/26/2008 |
| 7412535 | Method and system for caching fragments while avoiding parsing of pages that do not contain fragments A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device that contains a cache management unit, a fragment in the message body of the message is cached. Subse... | 08/12/2008 |
| 7409500 | Systems and methods for employing speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requ... | 08/05/2008 |
