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| Number | Title | Issue Date |
| 8135884 | Programmable interrupt routing system A method and apparatus for a programmable interrupt routing system is described. ... | 03/13/2012 |
| 8006006 | System and method for aggregating transmit completion interrupts Systems and methods for aggregating transmit completion interrupts for multiple packets are provided. A network device can include a buffer with multiple memory locations capable of temporarily storing a packet being transmitted across the network via the network de... | 08/23/2011 |
| 7953906 | Multiple interrupt handling method, devices and software A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an inter... | 05/31/2011 |
| 7899956 | System and method of reducing the rate of interrupts generated by a device in microprocessor based systems Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative ... | 03/01/2011 |
| 7836227 | Computer-readable recording medium having communication program recorded thereon, communication apparatus, and communication method A communication program causes a computer to perform communication processing of received packets in response to reception of interrupt processing, the interruption processing being a packet reception notification after the lapse of a predetermined holding time. The... | 11/16/2010 |
| 7802030 | Interrupt generation circuit for intermediate response to edge detection signal, when count value of main timer is less than pre-stored value The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective ... | 09/21/2010 |
| 7752353 | Signaling an interrupt request through daisy chained devices A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices ... | 07/06/2010 |
| 7743181 | Quality of service (QoS) processing of data packets The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method may include determining a queue of a plurality of queues causing an interrupt using contents of an interrup... | 06/22/2010 |
| 7721024 | System and method for exiting from an interrupt mode in a multiple processor system A system and method for interrupt processing includes a technique for exiting from interrupt mode in multiple processor systems. Those processors that were in a suspended or halt state immediately before entering the interrupt mode are released immediately with refe... | 05/18/2010 |
| 7676610 | Device and method for optimization of target host device process handling according to the status and the priority of the target host device process An input/output device stores host status information about the status of a host, and controls the input/output of data. By referring to the input/output information and the host status information, the device performs optimization control of selecting notification ... | 03/09/2010 |
| 7668982 | System and method for synchronous processing of media data on an asynchronous processor The present invention provides a method and system for processing media data on a host processor. The method and system involve receiving media data, generating clocking signals, transferring media data to host processor buffers, generating media transfer done inter... | 02/23/2010 |
| 7506082 | Data transferring system using USB and method thereof Data is transferred from a terminal to a computer over a USB cable. This is accomplished when the terminal transmits a control signal to the computer through a control line of a USB cable based on a value stored in a terminal register unit. The computer receives the... | 03/17/2009 |
| 7506083 | Method and system for identifying a peripheral device by a high priority device-specific notification handler Method and system for latency-independent peripheral device identification. The computer system receives an interrupt from a peripheral device via a communications port. In response, an interrupt notification message is posted to alert a notification handler, and co... | 03/17/2009 |
| 7454534 | Input circuit shared by multi signal sources An input circuit shared by multi signal sources each of which outputting a type of signals includes a processing unit (10). The processing unit includes a plurality of input pins (11) and an interrupt pin (12), each of the input pins connecting ... | 11/18/2008 |
| 7426589 | Network interface card for reducing the number of interrupts and method of generating interrupts A method of generating interrupts and a network interface card, which minimizes the number of times that interrupts are generated, are provided. The method includes receiving data frames; estimating a first and second time delay and counting a number of received dat... | 09/16/2008 |
| 7398340 | Method for the management of peripherals in an integrated circuit A microprocessor-based integrated circuit for smart cards includes an application software layer and a peripheral management system including an intermediate software layer to manage the hardware processes on peripherals of the integrated circuit that are called up ... | 07/08/2008 |
| 7386640 | Method, apparatus and system to generate an interrupt by monitoring an external interface In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a ... | 06/10/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7373435 | Extended input/output measurement block An Input/output (I/O) measurement block facility is provided that creates subchannel measurement blocks (comprising device busy values) related to performance of an I/O operation of a subchannel, wherein a device busy time value is a sum of time intervals when the s... | 05/13/2008 |
| 7370130 | Core logic device of computer system A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin... | 05/06/2008 |
| 7366809 | Pipelined stop, start, address byte, and data byte technique and circuit for IC logic system Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in ... | 04/29/2008 |
| 7363542 | Image formation apparatus and network system An operation detecting part detects operation of a power switch, and a backup device performs a backup operation enabling a predetermined amount of power supply even after the power switch has cut off the power supply. Upon detection of power cut off by the operatio... | 04/22/2008 |
| 7363390 | Techniques for managing a storage environment Techniques for managing a storage environment. According to an embodiment of the present invention, high-level application programming interfaces (APIs) are provided that can be used by applications such as storage management applications (e.g., ERM applications, SR... | 04/22/2008 |
| 7359782 | Vehicular impact reactive system and method System and method for reacting to an expected impact involving a vehicle including an anticipatory sensor system for determining that an impact involving the vehicle is about to occur prior to the impact and an impact responsive system coupled to the sensor system a... | 04/15/2008 |
| 7360109 | Measuring the interval of a signal using a counter and providing the value to a processor The present invention aims to be capable of properly measuring the cycle of an external signal even where a timer clock and a CPU clock are operated asynchronously. A timer circuit comprises a timer counter which counts a generation interval of an external signal in... | 04/15/2008 |
| 7343431 | Method, apparatus, and computer-readable medium for disabling BIOS-provided console redirection capabilities in the presence of an incompatible communications device Methods, systems, apparatus, and computer-readable media are provided for disabling a BIOS-provided console redirection facility in the presence of an incompatible device. According to the method, a determination is made as to whether a port has been enabled for uti... | 03/11/2008 |
| 7342321 | Bicycle electric power unit A bicycle electric power unit supplies electric power to a bicycle motor unit having a power source, a power source controller, a power source voltage detector, a first power source switch and a second power source switch. The power source controller turns off the f... | 03/11/2008 |
| 7339838 | Method and apparatus for supplementary command bus An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured t... | 03/04/2008 |
| 7337190 | Apparatus and method for hardware-based file system A hardware-based file system includes multiple linked sub-modules that perform functions ancillary to client data handling. Each sub-module is associated with a metadata cache. A doubly-rooted structure is used to store each file system object at successive checkpoi... | 02/26/2008 |
| 7328295 | Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated... | 02/05/2008 |
| 7328294 | Methods and apparatus for distributing interrupts The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics a... | 02/05/2008 |
| 7324068 | Chained image display apparatus having mutual examining function A chained image display apparatus having a mutual examining function where a plurality of image display apparatuses, controlled by a central control unit and connected in series, recognize interruption of power to an image display apparatus and correspondingly notif... | 01/29/2008 |
| 7321945 | Interrupt control device sending data to a processor at an optimized time An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit i... | 01/22/2008 |
| 7321592 | Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE Std 1394 serial buses An asynchronous control mechanism packet is used to send control messages and information to one or more bridge devices within a network of buses of devices. The asynchronous control mechanism packet is addressed to a device on one of the buses and is intercepted by... | 01/22/2008 |
| 7320044 | System, method, and computer program product for interrupt scheduling in processing communication Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a ... | 01/15/2008 |
| 7318112 | Universal interface simulating multiple interface protocols A universal interface interfaces between a variety of different data processing devices by the generation, storage, proper routing, and timed output of data signals to simulate behavior of a traditional interface device dedicated to that particular communications pr... | 01/08/2008 |
| 7315916 | Scratch pad block In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location wit... | 01/01/2008 |
| 7313672 | Intellectual property module for system-on-chip Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control... | 12/25/2007 |
| 7305588 | Testing the interrupt sources of a microprocessor A method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a default priority level and an associated memory, the interrupts having a... | 12/04/2007 |
| 7302512 | Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the vario... | 11/27/2007 |
