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| Number | Title | Issue Date |
| 8108585 | Crossbar circuitry and method of operation of such crossbar circuitry Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a d... | 01/31/2012 |
| 8108586 | Multi-core data processor To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bu... | 01/31/2012 |
| 8099540 | Reconfigurable circuit A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first con... | 01/17/2012 |
| 8095721 | Network switch and method of switching in network A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that transfer unit data in a specified format; a receiving side transfer unit t... | 01/10/2012 |
| 8095722 | Connection management in serial attached SCSI (SAS) expanders A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arb... | 01/10/2012 |
| 8090895 | Information processing system, information processing device, control method for information processing device, and computer-readable recording medium An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and... | 01/03/2012 |
| 8065465 | Mitigating main crossbar load using dedicated connections for certain traffic types One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradi... | 11/22/2011 |
| 8060682 | Method and system for multi-level switch configuration System and method to configure switch systems are disclosed. A switch system includes leaf modules with internal ports and spine modules with ports. A midplane includes first layers closer to a first side, second layers closer to a second side and third layers betwe... | 11/15/2011 |
| 8006026 | Multi-port memory and computer system provided with the same A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data bet... | 08/23/2011 |
| 7934046 | Access table lookup for bus bridge Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each ma... | 04/26/2011 |
| 7930464 | Scalable memory and I/O multiprocessor systems A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network compris... | 04/19/2011 |
| 7913028 | Data processing system having multiplexed data relaying devices, data processing aparatus having multiplexed data relaying devices, and a method of incorporating data relaying devices in data processing system having multiplexed data relaying devices When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device. ... | 03/22/2011 |
| 7908422 | System and method for a distributed crossbar network using a plurality of crossbars A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of... | 03/15/2011 |
| 7873775 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 01/18/2011 |
| 7822909 | Cross-bar switching in an emulation environment A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch in... | 10/26/2010 |
| 7797476 | Flexible connection scheme between multiple masters and slaves The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches. ... | 09/14/2010 |
| 7769942 | Cross-threaded memory system In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accord... | 08/03/2010 |
| 7752378 | Partition priority controlling system and method A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system... | 07/06/2010 |
| 7707350 | Bus interconnect switching mechanism A front side bus swizzle mechanism modifies the front side (address and data) bus on a chip so that, when the chip is positioned on one side of a printed circuit board, connection to a second chip located on the opposite side of the printed circuit board is simplifi... | 04/27/2010 |
| 7694064 | Multiple cell computer systems and methods In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect th... | 04/06/2010 |
| 7689758 | Dual bus matrix architecture for micro-controllers A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited ba... | 03/30/2010 |
| 7657693 | Router to use three levels of arbitration for a crossbar channel A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel ... | 02/02/2010 |
| 7640387 | Method and apparatus for implementing heterogeneous interconnects Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transf... | 12/29/2009 |
| 7620764 | System, apparatus and method for data path routing configurable to perform dynamic bit permutations A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In... | 11/17/2009 |
| 7603509 | Crossbar switch with grouped inputs and outputs A crossbar switch is optimized for area, performance, and power by grouping the data lines that comprise the input ports and output ports of the switch into a plurality of separate cross-point blocks. Each cross-point block contains a complete set of input and outpu... | 10/13/2009 |
| 7603508 | Scalable distributed memory and I/O multiprocessor systems and associated methods A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network compris... | 10/13/2009 |
| 7596653 | Technique for broadcasting messages on a point-to-point interconnect A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. ... | 09/29/2009 |
| 7594061 | Motherboard with multiple graphics interfaces A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The fir... | 09/22/2009 |
| 7590791 | Optimized switching method There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of ... | 09/15/2009 |
| 7587545 | Shared memory device A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory inte... | 09/08/2009 |
| 7584319 | Connection management in serial attached SCSI (SAS) expanders A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arb... | 09/01/2009 |
| 7584320 | Sliced crossbar architecture with no inter-slice communication A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory... | 09/01/2009 |
| 7581055 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 08/25/2009 |
| 7568063 | System and method for a distributed crossbar network using a plurality of crossbars A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of... | 07/28/2009 |
| 7568064 | Packet-oriented communication in reconfigurable circuit(s) A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein. ... | 07/28/2009 |
| 7565475 | Layered crossbar for interconnection of multiple processors and shared memories Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a... | 07/21/2009 |
| 7533211 | Cross-bar switching in an emulation environment A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch in... | 05/12/2009 |
| 7490189 | Multi-chip switch based on proximity communication A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between th... | 02/10/2009 |
| 7447828 | Programmable crossbar signal processor used as morphware A method includes providing a crossbar array including a programmable material layer, wherein the crossbar array is configured to function as part of a signal processing system and reprogramming at least one impedance value of the programmable material layer formed ... | 11/04/2008 |
| 7426709 | Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bu... | 09/16/2008 |
