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| Number | Title | Issue Date |
| 7917681 | Switch and network bridge apparatus A PCI Express switch which connects a plurality of peripheral devices to an arbitrary one of a plurality of CPUs through an Ethernet is constituted by a plurality of upstream and downstream PCI Express-network bridges, an Ethernet switch, and a system manager. Each ... | 03/29/2011 |
| 7761644 | Memory sharing arrangement for an integrated multiprocessor system A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed... | 07/20/2010 |
| 7689757 | Systems and methods for data transfer Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I... | 03/30/2010 |
| 7613864 | Device sharing An interconnect apparatus, for example a switch, supports PCI-Express. The apparatus has a first plurality of ports configurable as upstream ports, each connectable to a respective host, and at least one port configurable as a downstream port connectable to a device... | 11/03/2009 |
| 7610431 | Configuration space compaction In an interconnect apparatus for interconnecting at least one host to at least a plurality of presentation registers provide a presentation interface for the device to the host. The interconnect apparatus includes memory for holding the presentation registers and a ... | 10/27/2009 |
| 7447827 | Multi-port bridge device A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP b... | 11/04/2008 |
| 7443844 | Switched fabric mezzanine storage module A switched fabric mezzanine storage module (560) includes a storage module (562) and a switched fabric connector (563) coupled to the storage module. The storage module is coupled to directly communicate with a switched fabric (506), wher... | 10/28/2008 |
| 7444454 | Systems and methods for interconnection of multiple FPGA devices Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I... | 10/28/2008 |
| 7441066 | Managing a computer system having a plurality of partitions using a service processor The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or... | 10/21/2008 |
| 7440450 | Payload module having a switched fabric enabled mezzanine card A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of... | 10/21/2008 |
| 7428222 | Method of bus configuration to enable device bridging over dissimilar buses Several local IEEE1394 buses are bridged together over a second bus type to create a global bus wherein each local bus node is able to address nodes across the global bus without the local nodes being aware of the bridging operation. A bridging device operates by tr... | 09/23/2008 |
| 7426599 | Systems and methods for writing data with a FIFO interface Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I... | 09/16/2008 |
| 7376775 | Apparatus, system, and method to enable transparent memory hot plug/remove In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expande... | 05/20/2008 |
| 7376778 | Audio device The present invention provides a digital bus circuit comprising: a bus conductor having two sections each connected to a pass circuit, each bus section being connected to two bus interfaces for respective circuits; at least three of the bus interfaces comprising a t... | 05/20/2008 |
| 7373444 | Systems and methods for manipulating entries in a command buffer using tag information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master de... | 05/13/2008 |
| 7370225 | System and method for communicating a software-generated pulse waveform between two servers in a network A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between the two servers, the method including: transmitting a software-generated pulse waveform from the first serv... | 05/06/2008 |
| 7370130 | Core logic device of computer system A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin... | 05/06/2008 |
| 7366798 | Allocation of differently sized memory address ranges to input/output endpoints in memory mapped input/output fabric based upon determined locations of input/output endpoints An apparatus, program product and method in which a memory address space is allocated non-uniformly to IO resources in a memory mapped IO fabric based upon the locations of individual IO endpoints to which such IO resources are coupled. In a PCI-based environment, f... | 04/29/2008 |
| 7363404 | Creation and management of destination ID routing structures in multi-host PCI topologies System and method for managing routing of data in a distributed computing system, such as a distributed computing system that uses PCI Express protocol to communicate over an I/O fabric. A physical tree that is indicative of a physical configuration of the distribut... | 04/22/2008 |
| 7363408 | Interruption control system and method An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a ... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7360006 | Apparatus and method for managing voltage buses The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge c... | 04/15/2008 |
| 7349995 | Computing device with scalable logic block to respond to data transfer requests An apparatus a first processor which receives a data transfer request and generates a service command that corresponds to a scalable logic block required to respond to the data transfer request, and a server computer that receives the service command and scales the ... | 03/25/2008 |
| 7350002 | Round-robin bus protocol A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the dev... | 03/25/2008 |
| 7334118 | Method for resetting a processor involves receiving CPU reset trigger signal from BIOS A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when recei... | 02/19/2008 |
| 7334071 | Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows f... | 02/19/2008 |
| 7328300 | Method and system for keeping two independent busses coherent Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and th... | 02/05/2008 |
| 7325051 | Integrated storage appliance A system and method for providing an integrated storage appliance is disclosed. The storage appliance includes a storage subsystem, a process cluster coupled to the storage subsystem, and a customizable software stack that includes storage-access application so exec... | 01/29/2008 |
| 7325125 | Computer system for accessing initialization data and method therefor A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has ... | 01/29/2008 |
| 7324231 | Printer expansion method and apparatus The present invention is a computing system typically but not necessarily used in a printer, which includes a processor for managing operation of a print engine, expansion buses, and bridge devices between expansion buses. A bus bridge is described which can operate... | 01/29/2008 |
| 7320080 | Power management over switching fabrics A switching fabric handles transactions using a protocol that directs packets based on path routing information. Components participate in transactions using a protocol that issues packets based on physical location of a destination device over the switching fabric,... | 01/15/2008 |
| 7315964 | Digital signal measuring apparatus and traffic observing method A digital signal measuring apparatus comprises a bus probe unit for extracting a bus event occurring on a bus based on a digital bus signal on the bus of the system to be measured, a traffic measuring unit for counting the number of occurrences of bus event based on... | 01/01/2008 |
| 7315913 | CPU system, bus bridge, control method therefor, and computer system In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU 102 connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition ... | 01/01/2008 |
| 7284081 | Method and system for routing data between USB ports Aspects for high speed USB data routing are presented. The aspects include routing a data stream to and from USB I/O ports serially, and maintaining a frequency of the data stream during the routing. Additionally, a root port router is provided for the root port and... | 10/16/2007 |
| 7284082 | Controller apparatus and method for improved data transfer Embodiments of the invention include a controller apparatus, system and method for transferring data between data storage devices within a computer system. The inventive controller apparatus includes device interface logic for connecting the controller to a pluralit... | 10/16/2007 |
| 7281066 | Memory access system including support for multiple bus widths A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coup... | 10/09/2007 |
| 7281121 | Pipeline processing device and interrupt processing method At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention of an instruction decode stage in accordance with a setting address ou... | 10/09/2007 |
| 7281073 | Method for controlling interrupts and auxiliary control circuit An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt... | 10/09/2007 |
| 7275123 | Method and apparatus for providing peer-to-peer data transfer within a computing environment A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the ... | 09/25/2007 |
| 7275124 | Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the seco... | 09/25/2007 |
