Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8099539 | Method and system of a shared bus architecture A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a ... | 01/17/2012 |
| 7966440 | Image processing controller and image forming apparatus An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communic... | 06/21/2011 |
| 7934043 | Data processing apparatus for controlling access to a memory based upon detection of completion of a DMA bus cycle A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the fir... | 04/26/2011 |
| 7861026 | Signal relay device and method for accessing an external memory via the signal relay device A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus... | 12/28/2010 |
| 7818485 | IO processor An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for con... | 10/19/2010 |
| 7594058 | Chipset supporting a peripheral component interconnection express (PCI-E) architecture The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first UR... | 09/22/2009 |
| 7590788 | Controlling transmission on an asynchronous bus In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the reque... | 09/15/2009 |
| 7552268 | Method for improving bus utilization using predictive arbitration A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor will issue. The prediction is then used as a basis to mask or allow bus... | 06/23/2009 |
| 7451259 | Method and apparatus for providing peer-to-peer data transfer within a computing environment A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the ... | 11/11/2008 |
| 7433989 | Arbitration method of a bus bridge A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the system. The bus bridge supports a plurality of kinds of operations o... | 10/07/2008 |
| 7412550 | Bus system with protocol conversion for arbitrating bus occupation and method thereof A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereb... | 08/12/2008 |
| 7412555 | Ordering rule and fairness implementation In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter cir... | 08/12/2008 |
| 7408950 | Multiple node network and communication method within the network A multiple node network includes a plurality of terminal nodes. A management node manages the terminal nodes. A bus connects the respective terminal nodes and the management node to one another. The respective terminal nodes and the management node communicate with ... | 08/05/2008 |
| 7383395 | Storage device A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a ... | 06/03/2008 |
| 7380043 | Method and apparatus for arbitrating for serial bus access In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are co... | 05/27/2008 |
| 7373448 | Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to th... | 05/13/2008 |
| 7373457 | Cache coherence protocol for a multiple bus multiprocessor system A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, s... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7366816 | Method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of the data. A value representative of at least the number of buffers that... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366818 | Integrated circuit comprising a plurality of processing modules and a network and method for exchanging data using same An integrated circuit comprising a plurality of processing modules M, S and a network N; RN arranged for providing at least one connection between a first and at least one second module M, S is provided. Said connection supports transactions comprising outgoing mess... | 04/29/2008 |
| 7363411 | Efficient system management synchronization and memory allocation A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may ... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7360217 | Multi-threaded packet processing engine for stateful packet processing A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to acco... | 04/15/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7356652 | System and method for selectively storing bus information associated with memory coherency operations A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is established that identifies information pertaining to the bus snoop op... | 04/08/2008 |
| 7346725 | Method and apparatus for generating traffic in an electronic bridge via a local controller A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of ... | 03/18/2008 |
| 7340552 | Bus control system In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an iden... | 03/04/2008 |
| 7340545 | Distributed peer-to-peer communication for interconnect busses of a computer system There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second de... | 03/04/2008 |
| 7340551 | Bridge permitting access by multiple hosts to a single ported storage drive A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not sto... | 03/04/2008 |
| 7340740 | Cooperatively multitasking in an interrupt free computing environment Multitasking in a hardware interrupt free environment. Event indicators are employed to multitask between processes of the environment. Processes to be multitasked register with one another, and then during processing, one of the processes toggles an event indicator... | 03/04/2008 |
| 7337285 | Buffer allocation based upon priority An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer... | 02/26/2008 |
| 7337260 | Bus system and information processing system including bus system In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines co... | 02/26/2008 |
| 7334071 | Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows f... | 02/19/2008 |
| 7330904 | Communication of control information and data in client/server systems The invention provides a method and system in which a client/server system uses a NUMA communication link, possibly in combination with a byte serial communication link, to transfer relatively large blocks of data between client and server. The method and system pro... | 02/12/2008 |
| 7328300 | Method and system for keeping two independent busses coherent Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and th... | 02/05/2008 |
| 7328312 | Method and bus prefetching mechanism for implementing enhanced buffer control A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. Th... | 02/05/2008 |
| 7324231 | Printer expansion method and apparatus The present invention is a computing system typically but not necessarily used in a printer, which includes a processor for managing operation of a print engine, expansion buses, and bridge devices between expansion buses. A bus bridge is described which can operate... | 01/29/2008 |
| 7321985 | Method for achieving higher availability of computer PCI adapters Higher availability in a computer system is achieved by utilizing PCI (Peripheral Component Interconnect) adapters capable of dynamically switching between being controlled by a system processor and a specialized input/output processor (IOP). A method of fault recov... | 01/22/2008 |
