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| Number | Title | Issue Date |
| 8078785 | Host modules, electronic devices, electronic systems and data transmission method thereof A host module is disclosed, in which an interface is used to couple to at least an electronic device through a serial bus and comprises at least first and second ports. A detection unit reports that one of the first and second ports is enabled and the other is not e... | 12/13/2011 |
| 8015340 | Enhanced data communication by a non-volatile memory card A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data ... | 09/06/2011 |
| 7991938 | Bus width configuration circuit, display device, and method configuring bus width A display device communicating with a microcontrol unit by data, including: a panel with a plurality of pixels; and a display driver operating to drive the panel, in which the display driver includes: a data bus with a plurality of widths; a register storing an inde... | 08/02/2011 |
| 7949817 | Adaptive bus profiler An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via the adaptive bus can be determined. An adaptive bus profile can be dete... | 05/24/2011 |
| 7930462 | Interface controller that has flexible configurability and low cost In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate b... | 04/19/2011 |
| 7913023 | Specifying lanes for SAS wide port connections The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are che... | 03/22/2011 |
| 7882295 | Non-system bus width data transfer executable at a non-aligned system bus address Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method includes applying a FIFO buffer having a buffer width (e.g., determined us... | 02/01/2011 |
| 7844769 | Computer system having an apportionable data bus and daisy chained memory chips A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second ... | 11/30/2010 |
| RE41878 | Computer system with PCI express interface A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects ... | 10/26/2010 |
| 7793030 | Association of multiple PCI express links with a single PCI express port A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of... | 09/07/2010 |
| 7788439 | Asymmetrical bus for bus link width optimization of a graphics system A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional ... | 08/31/2010 |
| 7783816 | Computer capable of automatic bandwidth configuration according to I/O expansion card type A computer capable of automatic bandwidth configuration according to I/O expansion card (e.g., PCI-Express expansion card) type is provided. A motherboard of the computer includes an I/O expansion slot, a chipset, and a configuration setting circuit. When the I/O ex... | 08/24/2010 |
| 7721039 | System bus control apparatus, integrated circuit and data processing system The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer. A system bus control apparatus includes a system bus that is a path of data transferred from a bus master, a... | 05/18/2010 |
| 7707345 | Methods and apparatus for managing deadtime in feedback control queuing system Techniques for managing feedback control systems are provided. By way of example, a method of controlling performance of a managed system by a controller includes the following steps/operations. The controller issues a control value to the managed system to affect a... | 04/27/2010 |
| 7694060 | Systems with variable link widths based on estimated activity levels In some embodiments, a chip includes transmitters and receivers, and control circuitry. The control circuitry to cause some of the transmitters and receivers to be inoperative in response to an estimated activity level being in a first range, while others of the tra... | 04/06/2010 |
| 7657688 | Dynamically allocating lanes to a plurality of PCI express connectors Method, apparatus, and computer program products for dynamically allocating lanes to a plurality of PCI Express connectors are disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of th... | 02/02/2010 |
| 7624220 | Multisectional bus in radio base station and method of using such a radio base station A communication system has a monitor, memory and one or more resources. The memory is connected to the monitor by a bus and stores tasks and data. Each of the resources is connected to the monitor by the bus and performs a function or executes a program. The bus is ... | 11/24/2009 |
| 7620763 | Memory chip having an apportionable data bus A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is ded... | 11/17/2009 |
| 7606960 | Apparatus for adjusting a clock frequency of a variable speed bus An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor and increases or decreases the bus frequency in order to meet the band... | 10/20/2009 |
| 7552267 | Automatic detection of the bit width of a data bus A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performe... | 06/23/2009 |
| 7539809 | System and method for dynamic adjustment of an information handling systems graphics bus PCI Express bus utilization is monitored for one or more predetermined thresholds to adjust the width of the bus in accordance with the utilization to provide power savings with minimal impact on performance. For instance, a performance monitor of a graphics control... | 05/26/2009 |
| 7500043 | Array of data processing elements with variable precision interconnect Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column ar... | 03/03/2009 |
| 7490186 | Memory system having an apportionable data bus and daisy chained memory chips A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of ... | 02/10/2009 |
| 7480756 | Electronic data processing circuit that transmits packed words via a bus An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a... | 01/20/2009 |
| 7469311 | Asymmetrical bus A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional ... | 12/23/2008 |
| 7467251 | Flash memory data storage apparatus A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in... | 12/16/2008 |
| 7447824 | Dynamic lane management system and method A dynamic lane management system comprises at least one downstream device of a computer system configured to dynamically initiate a lane width re-negotiation operation with at least one upstream device of the computer system in response to a detection of at least on... | 11/04/2008 |
| 7447825 | PCI-E automatic allocation system A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of a first PCI-E slot with large lane width and a second PCI-E slot with... | 11/04/2008 |
| 7444452 | Computer system with a PCI express interface A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts wi... | 10/28/2008 |
| 7441064 | Flexible width data protocol A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is t... | 10/21/2008 |
| 7426597 | Apparatus, system, and method for bus link width optimization of a graphics system A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width d... | 09/16/2008 |
| 7426598 | Method for configuring transmitter power consumption A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The numbe... | 09/16/2008 |
| 7400326 | System and method for delivering multiple data streams via multiple buses Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerou... | 07/15/2008 |
| 7398344 | Plural interfaces in home network with first component having a first host bus width and second component having second bus width Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes). ... | 07/08/2008 |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a wr... | 05/20/2008 |
| 7376780 | Protocol converter to access AHB slave devices using the MDIO protocol A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initia... | 05/20/2008 |
| 7373447 | Multi-port processor architecture with bidirectional interfaces between busses A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couple... | 05/13/2008 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 05/13/2008 |
| 7370132 | Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock pow... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
