Bizarre Patents
A sealed crustless sandwich for providing a convenient sandwich without an outer crust which can be stored for long periods of time without a central filling from leaking outwardly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8112551 | Addressing scheme to allow flexible mapping of functions in a programmable logic array A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spac... | 02/07/2012 |
| 8095692 | Identification of devices in a medical device network and wireless data communication techniques utilizing device identifiers A fluid infusion system as described herein includes a number of local “body network” devices, such as an infusion pump, a handheld monitor or controller, a physiological sensor, and a bedside or hospital monitor. The body network devices can be configured to su... | 01/10/2012 |
| 8055805 | Opportunistic improvement of MMIO request handling based on target reporting of space requirements Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is ... | 11/08/2011 |
| 7996571 | Wireless coordination of apparatus interaction A system for implementing wireless control between apparatuses. In at least one scenario, an apparatus may, after an event (e.g., receiving wireless communication), create a wireless message based on the event, and may then send the wireless message to a peripheral ... | 08/09/2011 |
| 7979592 | Virtualization bridge device A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a fi... | 07/12/2011 |
| 7970956 | Graphics-processing system and method of broadcasting write requests to multiple graphics devices Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write r... | 06/28/2011 |
| 7945702 | Dynamic address mapping of a fibre channel loop ID The present invention is a method and a system for dynamic mapping of a fiber channel loop ID in an ALPA loop. Based on reserved address information for the fiber channel system and a number of select ID bits for a slot ID, a dynamic drive mapping table is created. ... | 05/17/2011 |
| 7941568 | Mapping a virtual address to PCI bus address Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are... | 05/10/2011 |
| 7941567 | Modular computer system and I/O module A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one ... | 05/10/2011 |
| 7908402 | Integrated multi-function point-of-load regulator circuit A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an addres... | 03/15/2011 |
| 7849229 | SPI addressing beyond 24-bits A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of un... | 12/07/2010 |
| 7849228 | Mechanisms for creation/deletion of linear block address table entries for direct I/O The present invention provides mechanisms that enable application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor. In one aspect of the present invention, a m... | 12/07/2010 |
| 7844745 | Alternate home subscriber server (HSS) node to receive a request if a first HSS node cannot handle said request This invention relates to methods and apparatus for providing a resilient network database. The invention relates particularly, but not exclusively, to the IP Multimedia Subsystem (IMS). The invention is directed to an interface for a database node comprising: a por... | 11/30/2010 |
| 7822878 | Device, system, and method for the automatic configuration of a network communications device Certain exemplary embodiments comprise a programmable cable further comprising a first end connectable to a PLC and a second end connectable to a network communications device, the network communications device further couplable to a user interface device. The progr... | 10/26/2010 |
| 7822879 | Methods for address assignment Methods for CEC logical address assignments and HDMI physical address assignments. Some embodiments determine a required HDMI physical address to be assigned to an upstream HDMI-CEC device and provide the required HDMI physical address. Other embodiments assign cons... | 10/26/2010 |
| 7805542 | Mobile unit attached in a mobile environment that fully restricts access to data received via wireless signal to a separate computer in the mobile environment Embodiments disclosed herein provide for an apparatus and method for input/output management in a mobile environment. One embodiment includes a mobile unit comprising at least one processor, a data bus interface and a computer readable memory persistently storing a ... | 09/28/2010 |
| 7793005 | Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an addres... | 09/07/2010 |
| 7739417 | Method, apparatus and system for seamlessly sharing a graphics card amongst virtual machines The present invention provides a virtual machine system and a method of accessing a graphics card. The virtual machine system includes a VMM, an SOS and at least one GOS, and further includes a resource converting module for performing IO address converting on graph... | 06/15/2010 |
| 7725609 | System memory device having a dual port A computing system having a plurality of processors including a first processor configured with an address port and a second processor configured with an address port, and a memory device having a first port configured as an address port and to alternatively interfa... | 05/25/2010 |
| 7694025 | Method and device for base address sorting and entry into base address registers A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address regist... | 04/06/2010 |
| 7685320 | Autonomous sequencing and fault spreading A power management system may be configured to allow digital information relating to the power management functions of sequencing and fault spreading to be passed between POL regulators using a standard multi-master multi-slave interface such as I2C bus i... | 03/23/2010 |
| 7660911 | Block-based data striping to flash memory In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA ... | 02/09/2010 |
| 7653758 | Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock signals are applied in parallel A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for applicat... | 01/26/2010 |
| 7653757 | Method for using a multi-master multi-slave bus for power management In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured wit... | 01/26/2010 |
| 7634586 | Device for concurrent limit validity check A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a multiplexer that is enabled to select content from a base address register in an array of base address registers, a comparator enabled comp... | 12/15/2009 |
| 7617331 | System and method of double address detection A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or service. ... | 11/10/2009 |
| 7571260 | CPU address decoding with multiple target resources A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least o... | 08/04/2009 |
| 7543081 | Use of NPort ID virtualization to extend the virtualization capabilities of the FC-SB-3 protocol and other protocols A computer implemented method, data processing system, and computer usable program code are provided for using identifier virtualization to extend the virtualization capabilities of protocols. A determination is made as to whether a logical entity requires a unique ... | 06/02/2009 |
| 7539782 | Method of virtualizing I/O resources in a computer system A method of virtualizing hardware resources in a multiprocessor computing environment is provided. Each resource is provided a resource address. A hardware resource map is provided to store virtual resource addresses and physical resource addresses. Remapping hardwa... | 05/26/2009 |
| 7533191 | Methods and arrangements for devices to share a common address on a bus Methods and arrangements for devices to share a common address on a bus are disclosed. Embodiments may comprise a host for medium management and one or more client devices coupled with a communication medium. The host and/or one or more of the client devices may com... | 05/12/2009 |
| 7464188 | Computer system controlling accesses to storage apparatus Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is cons... | 12/09/2008 |
| 7464189 | System and method for creation/deletion of linear block address table entries for direct I/O A method that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor is provided. In one aspect of the method, a mechanism is provided for handli... | 12/09/2008 |
| 7444437 | Input/output device and method of setting up identification information in input/output device An input/output device and a method of setting up identification information for an input/output device, to confirm which slot of which device enclosure each unit is mounted in, within a short time, from a map, and execute quick access to the unit. A unit mounted on... | 10/28/2008 |
| 7444440 | Method and device for providing high data rate for a serial peripheral interface An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. ... | 10/28/2008 |
| 7441050 | Data processing system, data processing method, computer-readable storage medium, and disk drive In a data processing system that processes serial data transferred from a processor formed as one chip and transmits the resultant data to another chip, a data output processing unit that processes serial data transferred from a single processor or a plurality of pr... | 10/21/2008 |
| 7426607 | Memory system and method of operating memory system A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the m... | 09/16/2008 |
| 7426583 | Method and circuit for decoding an address of an address space Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ran... | 09/16/2008 |
| 7424554 | Method of and system for changing the address of a disk array enclosure An apparatus for setting an enclosure address in a computer system having a plurality of enclosures includes at least one enclosure address control device including input means for changing the enclosure address of an associated enclosure of the plurality of enclosu... | 09/09/2008 |
| 7421515 | Method and system for communications network A system and method of operation are provided for using a network interface to process incoming messages sent by a client device to a network server. The network interface includes a First-In-First-Out (FIFO) buffer for assembling the incoming messages from a serial... | 09/02/2008 |
| 7420701 | Systems and methods for providing automatic language switching Systems and methods for accurately recognizing a language format of an input imaging data stream when no explicit language switch is present. A sniffer process is initiated when an imaging device receives an input imaging data stream. The sniffer process analyzes an... | 09/02/2008 |
