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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8156260 | Data transfer device and method for selecting instructions retained in channel unit based on determined priorities due to the number of waiting commands/instructions A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to correspond to the other devices, the channel units retaining DMA transfer in... | 04/10/2012 |
| 8122164 | Information processing apparatus having first DMA controller and second DMA controller wherein selection circuit determines which DMA will perform data transfer based on higher data transfer performance Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer c... | 02/21/2012 |
| 8086766 | Support for non-locking parallel reception of packets belonging to a single memory reception FIFO A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network re... | 12/27/2011 |
| 8051223 | System and method for managing memory using multi-state buffer representations In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer con... | 11/01/2011 |
| 7769919 | Protecting computer memory from simultaneous direct memory access operations using active and inactive translation tables A method, apparatus, and program product access memory resources of a computer using a group of direct access memory (DMA) devices. A first DMA device is designated a primary device after association with an active translation table (ATT), while a second DMA device ... | 08/03/2010 |
| 7716392 | Computer system having an I/O module directly connected to a main storage for DMA transfer A computer system includes a CPU (Central Processing Unit) and a main storage interconnected by a bus to the CPU. The I/O module for transferring received data and data to be transmitted to and from an external unit is directly connected to the main storage, which s... | 05/11/2010 |
| 7636800 | Method and system for memory address translation and pinning A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address... | 12/22/2009 |
| 7523229 | Memory protection during direct memory access An I/O controller to which an I/O device is connected includes a DMA controller (DMAC) and an access control unit (ACU). The DMAC executes DMA transfer in accordance with data transfer control information set in a control/status register by a user process. The ACU l... | 04/21/2009 |
| 7493425 | Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a portion, or all, of its associated System Memory to a shared PCI Adapt... | 02/17/2009 |
| 7444440 | Method and device for providing high data rate for a serial peripheral interface An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. ... | 10/28/2008 |
| 7444441 | Device including means for transferring information indicating whether or not the device supports DMA A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... | 10/28/2008 |
| 7430621 | Multiple channel data bus control for video processing A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on select... | 09/30/2008 |
| 7428624 | Host computer system and storage system having a bandwidth management function for storage volumes Provided is a computer system including a plurality of data storage apparatus and manages a bandwidth of a data storage apparatus according to an attribute of a storage volume. A storage system includes an interface for processing access to the storage volume from a... | 09/23/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7383363 | Method and apparatus for interval DMA transfer access A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a pe... | 06/03/2008 |
| 7383336 | Distributed shared resource management A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethor... | 06/03/2008 |
| 7380115 | Transferring data using direct memory access A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the prima... | 05/27/2008 |
| 7373467 | Storage device flow control A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and assembling the plurality of data sources in a prioritized list. The method also includes removing lowest prior... | 05/13/2008 |
| 7370123 | Information processing apparatus A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A ... | 05/06/2008 |
| 7370135 | Band configuration agent for link based computing system A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command d... | 05/06/2008 |
| RE40261 | Apparatus and method of partially transferring data through bus and bus master control device A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; d... | 04/22/2008 |
| 7356671 | SoC architecture for voice and video over data network applications A system-on-chip (SoC) for voice and video over data network applications includes a first and a second general purpose processors and a plurality of coprocessors. The coprocessors include: a VCODEC engine for video compression/decompression, a security engine for d... | 04/08/2008 |
| 7346778 | Security method and apparatus for controlling the data exchange on handheld computers A method and system for protecting portable computer data from unauthorized transfer or using portable computers to download unauthorized data. The invention is applicable to any computer capable of transferring data, but in one embodiment a portable computer is des... | 03/18/2008 |
| 7340743 | Masterless locks in a multi-node environment A method, system, application programming interface, computer system, and computer program product to provide locks for controlling access to data by nodes in a multi-node environment while minimizing messages sent between nodes. Based upon knowledge of lock usage i... | 03/04/2008 |
| 7330914 | DMA controller, DMA control method and DMA control program The present invention is a DMA controller that accesses a transfer source and a transfer destination of a DMA transfer via a bus, that chains a plurality of data segments in the transfer source according to an instruction by an external initiator, and that performs ... | 02/12/2008 |
| 7302699 | Logged-in device and log-in device A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous lo... | 11/27/2007 |
| 7302541 | System and method for switching access paths during data migration The present invention suppresses the generation of redundant I/O and improves the response to the host during data migration. When migrating data from the migration source volume to the migration destination volume, the access destination of the host is switched to ... | 11/27/2007 |
| 7302503 | Memory access engine having multi-level command structure A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer fi... | 11/27/2007 |
| 7296100 | Packet buffer management apparatus and method A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system ... | 11/13/2007 |
| 7284061 | Obtaining temporary exclusive control of a device Remotely obtaining exclusive control of a device by remotely establishing communication with the device over a network, requesting to obtain remote exclusive control of the device's capabilities, and determining whether remote exclusive control of the device's capab... | 10/16/2007 |
| 7275097 | System and method for analyzing input/output activity on local attached storage A system, method and computer program product for analyzing file I/O activity on local attached storage devices within a computer network is provided. In an embodiment, a software agent executes on one or more servers within the network, and monitors the I/O activit... | 09/25/2007 |
| 7269745 | Methods and apparatus for composing an identification number Methods and apparatus for producing an electronic ID number include modifying at least one physical bit element from among each of at least first and second groups of physical bit elements, each physical bit element of each group having a first physical state in whi... | 09/11/2007 |
| 7260688 | Method and apparatus for controlling access to memory circuitry Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality... | 08/21/2007 |
| 7259876 | Image processing apparatus, and, control method and control device therefor A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data into the first storage, a data transfer of the said image data from the ... | 08/21/2007 |
| 7260664 | Interrupt mechanism on an IO adapter that supports virtualization A mechanism for handling event notifications or interrupts in a logically partitioned computing system having IO adapters that support adapter virtualization are provided. A virtual adapter associated with a physical IO adapter detects an event, identifies a logical... | 08/21/2007 |
| 7254651 | Scheduler for a direct memory access device having multiple channels A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also ... | 08/07/2007 |
| 7251759 | Method and apparatus to compare pointers associated with asynchronous clock domains A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are no... | 07/31/2007 |
| 7251700 | Time-to-live timeout on a logical connection from a connection cache Techniques for utilizing a time-to-live timeout on a logical connection to a resource (e.g., a database) from a cache are provided. When a logical connection to the resource is obtained, a timeout is set specifying the amount of time the logical connection can be ut... | 07/31/2007 |
| 7246205 | Software controlled dynamic push cache Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether th... | 07/17/2007 |
| 7246102 | Method of improving the lookup performance of three-type knowledge base searches A decision tree, representing a knowledge base, is segmented into at least two decision tree portions. The lower portion includes the tree entry point and is stored in a memory element with a faster access time than the upper portion, which includes the terminating ... | 07/17/2007 |
