Quotables
"Rail travel at high speeds is not possible because passengers, unable to breathe, would die of asphyxia."
Dionysius Lardner, Professor of Natural Philosophy and Astronomy at University College, London ; 1830
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| Number | Title | Issue Date |
| 8392643 | Data processing device, semiconductor integrated circuit device, and abnormality detection method A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection circuit. The interrupt counter increments a count value based on an interrupt... | 03/05/2013 |
| 8321614 | Dynamic scheduling interrupt controller for multiprocessors Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the multiprocessor computing system can be maintained. Cache state information associa... | 11/27/2012 |
| 8312195 | Managing interrupts using a preferred binding between a device generating interrupts and a CPU A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The interrupt controller identifies a preferred CPU associated with the device ... | 11/13/2012 |
| 8312196 | Dual processor system and method for using the same A dual processor system comprises a first processor, a second processor, and a dual-ported random access memory (DPRAM). When the first processor stores data to be processed by the second processor to the DPRAM and writes interrupt data to the DPRAM, the DPRAM gener... | 11/13/2012 |
| 8145820 | Multiprocessor system and computer program product In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when... | 03/27/2012 |
| 8117368 | System management interrupt interface wrapper In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format... | 02/14/2012 |
| 8055828 | Electronic power management system An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for in... | 11/08/2011 |
| 8032681 | Processor selection for an interrupt based on willingness to accept the interrupt and on priority In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to re... | 10/04/2011 |
| 8010727 | System management interrupt interface wrapper In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format... | 08/30/2011 |
| 7984218 | Processor, electronic apparatus, interruption control method and interruption control program A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1n which outputs an interrupt request when an interrupt source is generat... | 07/19/2011 |
| 7958296 | System management and advanced programmable interrupt controller Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the... | 06/07/2011 |
| 7949813 | Method and system for processing status blocks in a CPU based on index values and interrupt mapping Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status block has been processed by at least one CPU based on comparing a val... | 05/24/2011 |
| 7899966 | Methods and system for interrupt distribution in a multiprocessor system A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an inter... | 03/01/2011 |
| 7877535 | Processor and interrupt handling method Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode... | 01/25/2011 |
| 7827339 | System management interrupt interface wrapper In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format... | 11/02/2010 |
| 7730249 | Device control apparatus that calls an operating system to control a device In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls on... | 06/01/2010 |
| 7610426 | System management mode code modifications to increase computer system security Methods for processing more securely. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of p... | 10/27/2009 |
| 7581052 | Approach for distributing multiple interrupts among multiple processors A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the proces... | 08/25/2009 |
| 7562173 | Handling shared interrupts in bios under a virtualization technology environment A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT) environment. In some embodiments, the custom interrupt service routi... | 07/14/2009 |
| 7546406 | Virtualization of a global interrupt queue A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logi... | 06/09/2009 |
| 7464211 | Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment A method for handling multiple system management interrupt (SMI) events in a multiprocessor system. The method comprises a first set of one or more processors in the multiprocessor system receiving a first SMI event. The first set of processors then enter an SMI han... | 12/09/2008 |
| 7433985 | Conditional and vectored system management interrupts An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is bro... | 10/07/2008 |
| 7415561 | Computer for dynamically determining interrupt delay In a computer having a unit for outputting an interrupt request to a processor, a delay condition from occurrence of an interrupt event to issue of an interrupt request to the processor can be dynamically determined depending on the processor load status, etc. The i... | 08/19/2008 |
| 7409483 | Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to proper... | 08/05/2008 |
| 7386646 | System and method for interrupt distribution in a multithread processor A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is executed, the set of thread processors are affected. While executing th... | 06/10/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
| 7363409 | Interrupt control system and method for reducing interrupt latency An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable ... | 04/22/2008 |
| 7363412 | Interrupting a microprocessor after a data transmission is complete A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives ... | 04/22/2008 |
| 7363411 | Efficient system management synchronization and memory allocation A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may ... | 04/22/2008 |
| 7360101 | Apparatus and method for controlling CPU speed transition An apparatus and method for controlling CPU speed transition can use an SMI (System Management Interrupt) signal to perform speed transition of a CPU of a computer such as a notebook computer. However, if the bus master device is in the active state, a control opera... | 04/15/2008 |
| 7353312 | Method and apparatus for detecting conditions for blocking a CPU's receipt of signals returned from a peripheral device A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in r... | 04/01/2008 |
| 7350065 | Method, apparatus and program storage device for providing a remote power reset at a remote server through a network connection A method, apparatus and program storage device for performing a remote power reset at a remote server through a network connection is disclosed. A power reset procedure is pinned to memory at a remote server. The remote server listens for a call specifying the power... | 03/25/2008 |
| 7350006 | System and method of interrupt handling A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least importa... | 03/25/2008 |
| 7350007 | Time-interval-based system and method to determine if a device error rate equals or exceeds a threshold error rate An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a processor. The interrupt handler executes, upon expiration of a time period, ... | 03/25/2008 |
| 7340740 | Cooperatively multitasking in an interrupt free computing environment Multitasking in a hardware interrupt free environment. Event indicators are employed to multitask between processes of the environment. Processes to be multitasked register with one another, and then during processing, one of the processes toggles an event indicator... | 03/04/2008 |
| 7334136 | Virtual machine with securely distributed bytecode verification A system for executing a software application comprising a plurality of hardware independent bytecodes is provided comprising a computing system that generates bytecodes, a virtual machine, remote to the computing system, that receives a plurality of bytecodes from ... | 02/19/2008 |
| 7313797 | Uniprocessor operating system design facilitating fast context switching A task stack and a context pointer in a task control block (TCB) are implemented to provide more efficient context switching. Additionally, multiple routines each of which saves or restores a certain combination of volatile registers is implemented. A task can store... | 12/25/2007 |
| 7287281 | Send blocking system and method A method includes hooking a send operating system function, originating a call to the send operating system function with a call module to send the content of a send buffer, stalling the call, and determining whether the call module or a copy of the call module are ... | 10/23/2007 |
| 7281075 | Virtualization of a global interrupt queue A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logi... | 10/09/2007 |
| 7275122 | Method and system for maintaining a desired service level for a processor receiving excessive interrupts A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during which interrupts will be measured for a processor. The amounts of time spe... | 09/25/2007 |
