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| Number | Title | Issue Date |
| 8145819 | Method and system for stealing interrupt vectors A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block... | 03/27/2012 |
| 8074006 | Abnormal status detecting method of interrupt pins An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt s... | 12/06/2011 |
| 8010726 | Data processing apparatus and method for handling interrupts A data processing apparatus and method for handling interrupts is provided, the apparatus having an interrupt controller operable to receive interrupts generated by a number of interrupt sources, and to determine based on predetermined criteria whether to output an ... | 08/30/2011 |
| 7975087 | Control and communication unit between a terminal and a microcircuit card A control and communication unit is provided between a terminal and at least one microcircuit card. The unit includes a control module for a number of input signals to the card; a module for generation of a number of time diagrams for the card communication protocol... | 07/05/2011 |
| 7953915 | Interrupt dispatching method in multi-core environment and multi-core processor Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integ... | 05/31/2011 |
| 7953914 | Clearing interrupts raised while performing operating system critical tasks Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having t... | 05/31/2011 |
| 7913017 | Embedded system and interruption handling method An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service r... | 03/22/2011 |
| 7873770 | Filtering and remapping interrupts In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base address of a device table, wherein a given input/output (I/O) device ... | 01/18/2011 |
| 7752371 | System and method for interrupt abstraction A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrup... | 07/06/2010 |
| 7721034 | System and method for managing system management interrupts in a multiprocessor computer system A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a s... | 05/18/2010 |
| 7634604 | Systems for generating synchronized events and images A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender deter... | 12/15/2009 |
| 7512730 | Method for dynamically allocating interrupt pins A method for dynamically allocating interrupt pins is provided. The present method is used for allocating a plurality of interrupt pins of a control chip. In the present method, a hardware routing table is read first and a plurality of slots that have used the inter... | 03/31/2009 |
| 7506091 | Interrupt controller utilising programmable priority values An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 pr... | 03/17/2009 |
| 7444451 | Adaptive interrupts coalescing system with recognizing minimum delay packets The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, an... | 10/28/2008 |
| 7426728 | Reducing latency, when accessing task priority levels One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt ... | 09/16/2008 |
| 7421692 | Real time control system A real-time control system for executing exactly a cyclic task, preventing a delay of the processing start time due to accumulation of a plurality of overhead times, thereby executing control enabling a more detailed response and control enabling a quick and reliabl... | 09/02/2008 |
| 7415558 | Communication steering for use in a multi-master shared resource system New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) stan... | 08/19/2008 |
| 7415560 | Method of automatically monitoring computer system debugging routine A monitor method of computer system is provided, applying within an interrupt service routine. According to the application of interrupt service, when the interrupt controller sends an interrupt signal to the CPU, the CPU executes a corresponding interrupt service r... | 08/19/2008 |
| 7395434 | Method for secure storage and verification of the administrator, power-on password and configuration information A computer includes a processor, an input device and a read only memory (“ROM”). One or more passwords are flashed in the ROM in encoded form. The encoding process may include any well-known encryption or hash process. The password may include a power-on passwor... | 07/01/2008 |
| 7373446 | Method and system for dynamically patching an operating system's interrupt mechanism In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the hos... | 05/13/2008 |
| 7370130 | Core logic device of computer system A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin... | 05/06/2008 |
| 7366814 | Heterogeneous multiprocessor system and OS configuration method thereof Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt... | 04/29/2008 |
| 7363410 | Flexible interrupt handling methods for optical network apparatuses with multiple multi-protocol optical networking modules An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol... | 04/22/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7359998 | Low-power CD-ROM player with CD-ROM subsystem for portable computer capable of playing audio CDs without supply energy to CPU A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating cir... | 04/15/2008 |
| 7350006 | System and method of interrupt handling A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least importa... | 03/25/2008 |
| 7340596 | Embedded processor with watchdog timer for programmable logic A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (... | 03/04/2008 |
| 7340447 | Partitioning data access requests A system with multiple data stores receives a data access request that includes one or more variables. The system determines which data store can service the data access request by using mappings of the variables to the data stores in order to evaluate whether parti... | 03/04/2008 |
| 7340740 | Cooperatively multitasking in an interrupt free computing environment Multitasking in a hardware interrupt free environment. Event indicators are employed to multitask between processes of the environment. Processes to be multitasked register with one another, and then during processing, one of the processes toggles an event indicator... | 03/04/2008 |
| 7337254 | Information processing system and method of controlling the same An information processing system operating in response to a remote control signal transmitted from a remote controller, the information processing system including a remote signal receiver to receive the remote control signal; an interrupt generator to generate a sy... | 02/26/2008 |
| 7333946 | Ticketing with printing option A method of purchasing and printing a ticket from a wireless device. A wireless device selects and pays for a ticket from a wireless terminal. The ticket is printed at a later time in order to reduce the possibility of the losing it. A printing device is selected by... | 02/19/2008 |
| 7321947 | Systems and methods for managing multiple hot plug operations A method for managing multiple hot plug operations in an information handling system is provided. An instruction for initiating a new hot plug operation is received, the new hot plug operation including one or more hot plug system management interrupts (SMIs). Anoth... | 01/22/2008 |
| 7320044 | System, method, and computer program product for interrupt scheduling in processing communication Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a ... | 01/15/2008 |
| 7315911 | Method for efficient inter-processor communication in an active-active RAID system using PCI-express links A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it inter... | 01/01/2008 |
| 7305588 | Testing the interrupt sources of a microprocessor A method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a default priority level and an associated memory, the interrupts having a... | 12/04/2007 |
| 7302503 | Memory access engine having multi-level command structure A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer fi... | 11/27/2007 |
| 7302301 | Method for monitoring an automation system A method and a system for monitoring and determining preceding states of at least one terminal of an automation system are provided. The automation system includes one or more terminals (1, 2), each of which can assume two or more states and each of which out... | 11/27/2007 |
| 7302511 | Chipset support for managing hardware interrupts in a virtual machine system In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a dist... | 11/27/2007 |
| 7289531 | Network-system, management-system, method and computer program product Provided is a management-system for use in a network environment including a first and second IP networks and a transport network which connects the first and second IP networks. The management system includes: a converter for optimizing a path in an IP-domain via a... | 10/30/2007 |
| 7287112 | Dynamic reconfiguration interrupt system and method The present invention system and method enables dynamic reconfiguration of an electronic device with appropriate interrupts in a convenient and efficient manner. A plurality of internal peripherals, an interconnecting component and the external coupling ports are pr... | 10/23/2007 |
