Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 7996595 | Interrupt arbitration for multiprocessors Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determine... | 08/09/2011 |
| 7711882 | Interrupt jitter suppression A data processing apparatus comprises a processing unit which is responsive to a plurality of interrupt signals to carry out a corresponding interrupt routine. On receipt of an interrupt signal, the processing unit stores data values from a plurality of registers on... | 05/04/2010 |
| 7627705 | Method and apparatus for handling interrupts in embedded systems An Interrupt Processor is provided in an embedded system to handle interrupts generated in the system. The function of the interrupt processor is to handle interrupts and execute interrupt routines. It performs code execution for interrupts which require immediate r... | 12/01/2009 |
| 7523240 | Interrupt controller and interrupt control method An interrupt controller superior in maintenance performance and expandability. An interrupt controller 10 comprises a queue circuit 11 that holds channel numbers corresponding to interrupt inputs in the order of priority levels, and a queue control cir... | 04/21/2009 |
| 7395360 | Programmable chip bus arbitration logic Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bu... | 07/01/2008 |
| 7284080 | Memory bus assignment for functional devices in an audio/video signal processing system The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bu... | 10/16/2007 |
| 7248568 | Apparatus for detecting hidden nodes in a wireless network A wireless network according to the present invention includes a plurality of nodes that transmit and receive radio frequency (RF) signals. An access point broadcasts and receives radio frequency (RF) signals, wirelessly communicates with the plurality of nodes, gen... | 07/24/2007 |
| 7222251 | Microprocessor idle mode management system An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock ... | 05/22/2007 |
| 7206884 | Interrupt priority control within a nested interrupt system A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent probl... | 04/17/2007 |
| 7149831 | Batch processing of interrupts A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performin... | 12/12/2006 |
| 7133951 | Alternate set of registers to service critical interrupts and operating system traps A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor a... | 11/07/2006 |
| 7120718 | Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interru... | 10/10/2006 |
| 7117285 | Method and system for efficiently directing interrupts A method and system for efficiently directing interrupts is disclosed. In a computer system having multiple processors, a computer implemented method, upon detecting an interrupt directed to one of the processors, determines a policy for efficiently handling the int... | 10/03/2006 |
| 7080188 | Method and system for embedded disk controllers A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and ... | 07/18/2006 |
| 7043729 | Reducing interrupt latency while polling Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pe... | 05/09/2006 |
| 7043584 | Interrupt prioritization in a digital disk apparatus In an digital video disk player the timely acquisition of specific data types is particularly important during trick mode operation. During trick modes a controller can provide enhanced control capability by employing interrupt requests having priorities that differ... | 05/09/2006 |
| 7039771 | Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers A serial port controller in an embedded disk drive controller is provided. The serial port controller includes a state machine that can access protocol information regarding plural devices operationally coupled to the serial port controller; a first register that ca... | 05/02/2006 |
| 7028123 | Microcomputer, has selection circuit to select either testing-purpose interrupt request signal or interrupt request selection signal based on delayed selection signal, where selected signals are sent to interrupt controller In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effecti... | 04/11/2006 |
| 6993685 | Technique for testing processor interrupt logic In a technique for testing processor interrupt logic, interrupts are sent to a microprocessor under test in a random order to test the processor interrupt logic of the microprocessor under test. The processor interrupt logic is considered to have failed the test if ... | 01/31/2006 |
| 6981133 | Zero overhead computer interrupts with task switching The invention constitutes a unique hardware zero overhead interrupt and task change mechanism for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs comple... | 12/27/2005 |
| 6971043 | Apparatus and method for accessing a mass storage device in a fault-tolerant server An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass ... | 11/29/2005 |
| 6965528 | Memory device having high bus efficiency of network, operating method of the same, and memory system including the same A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plu... | 11/15/2005 |
| 6928502 | Method and apparatus for processing interrupts at dynamically selectable prioritization levels A method and apparatus are described by which interrupts from a source may be processed at a dynamically selectable level of priority. A system that has at least two different interrupt request connections, and that responds to interrupts asserted on the different c... | 08/09/2005 |
| 6898262 | Programmable controller An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing sect... | 05/24/2005 |
| 6851006 | Interruption handler-operating system dialog for operating system handling of hardware interruptions Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, ar... | 02/01/2005 |
| 6772260 | Device for and method of generating interrupt signals An interrupt signal generating device comprises interrupt detection units (20) each adapted to output a detection signal (DET-1 to DET-n) in response to a respective input signal (IN-1 to IN-n) representing an interrupt event; and an interrupt h... | 08/03/2004 |
| 6718413 | Contention-based methods for generating reduced number of interrupts Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or... | 04/06/2004 |
| 6581119 | Interrupt controller and a microcomputer incorporating this controller To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data i... | 06/17/2003 |
| 6502152 | Dual interrupt vector mapping A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high e... | 12/31/2002 |
| 6279067 | Method and apparatus for detecting interrupt requests in video graphics and other systems A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pendi... | 08/21/2001 |
| 6219741 | Transactions supporting interrupt destination redirection and level triggered interrupt semantics In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data rep... | 04/17/2001 |
| 6205507 | Memory coherency in a processor-to-bus cycle in a multi-processor system In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the i... | 03/20/2001 |
| 6151664 | Programmable SRAM and DRAM cache interface with preset access priorities A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on the processor and one portion on the cache. A designer can ... | 11/21/2000 |
| 6148361 | Interrupt architecture for a non-uniform memory access (NUMA) data processing system A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that... | 11/14/2000 |
| 6145048 | Method of processing system management interrupt requests A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced ... | 11/07/2000 |
| 6115776 | Network and adaptor with time-based and packet number based interrupt combinations A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mecha... | 09/05/2000 |
| 6105102 | Mechanism for minimizing overhead usage of a host system by polling for subsequent interrupts after service of a prior interrupt An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a pr... | 08/15/2000 |
| 6081867 | Software configurable technique for prioritizing interrupts in a microprocessor-based system A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indic... | 06/27/2000 |
| 6070221 | Interrupt controller An interrupt controller comprises a plurality of interrupt handling elements that are given different identification numbers for identification to which priorities are assigned. A first priority encoder accepts a plurality of level signals which are given... | 05/30/2000 |
| 6002877 | Interrupt control method for controlling an interrupt from a peripheral device to a processor A method for controlling an interrupt from a peripheral device to a processor, the peripheral device including at least an interrupt control unit, an interrupt request level holding unit, and an interrupt vector holding unit, which includes the steps of: ... | 12/14/1999 |
