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| Number | Title | Issue Date |
| 8166223 | Apparatuses to provide a message signaled interrupt to generate a PCI express interrupt Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to proper... | 04/24/2012 |
| 8151027 | System management mode inter-processor interrupt redirection A method, processor, and system are disclosed. In one embodiment method includes a first processor core among several processor cores entering into a system management mode. At least one of the other additional processor cores apart from the first processor core rem... | 04/03/2012 |
| 8122176 | System and method for logging system management interrupts In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of... | 02/21/2012 |
| 8117367 | Processor system with an application and a maintenance function A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors ha... | 02/14/2012 |
| 8069290 | Processing system operable in various execution environments A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at... | 11/29/2011 |
| 8032679 | Device and method for controlling network processing mode, and non-transitory computer-readable medium recording program for controlling network processing mode A network control device including a network controller for transmitting/receiving data through a network and storing received data in a storage and a network processor for processing data stored in the storage is provided with a usage information acquiring section ... | 10/04/2011 |
| 8001309 | Method and system for grouping interrupts from a time-dependent data storage system A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage means with an indicator of an event associated with the part, generati... | 08/16/2011 |
| 7991933 | Synchronizing processors when entering system management mode A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the... | 08/02/2011 |
| 7979619 | Emulating a line-based interrupt transaction in response to a message signaled interrupt Methods, systems, apparatuses and program products are disclosed for managing interrupt services in hypervisor and hypervisor-related environments in Message Signaled Interrupts are emulated as other type(s) of interrupt. According to an aspect of the present... | 07/12/2011 |
| 7962679 | Interrupt balancing for multi-core and power A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts an... | 06/14/2011 |
| 7934036 | Interrupt-related circuits, systems, and processes An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an inte... | 04/26/2011 |
| 7788433 | Microprocessor apparatus providing for secure interrupts and exceptions An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocess... | 08/31/2010 |
| 7765352 | Reducing core wake-up latency in a computer system A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a firs... | 07/27/2010 |
| 7761638 | Dynamic creation of low-level interfaces In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the hos... | 07/20/2010 |
| 7743194 | Driver transparent message signaled interrupts Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to proper... | 06/22/2010 |
| 7730248 | Interrupt morphing and configuration, circuits, systems and processes An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) ... | 06/01/2010 |
| 7689747 | Systems and methods for an augmented interrupt controller and synthetic interrupt sources Various embodiments of the present invention are directed to augmented interrupt controllers (AICs) and to synthetic interrupt sources (SISs) providing richer interrupt information (or “synthetic interrupts” or “SIs”). The AIC and SIS provide efficient means... | 03/30/2010 |
| 7689748 | Event handler for context-switchable and non-context-switchable processing tasks Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signa... | 03/30/2010 |
| 7603504 | Reducing core wake-up latency in a computer system A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a firs... | 10/13/2009 |
| 7433986 | Minimizing ISR latency and overhead The capability to handle the 100 μs RPR interrupt and similar interrupts is provided by servicing selected interrupts outside of the operating system. This drastically reduces the latency and overhead associated with servicing the interrupt. A method of handling an... | 10/07/2008 |
| 7433985 | Conditional and vectored system management interrupts An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is bro... | 10/07/2008 |
| 7424563 | Two-level interrupt service routine A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler i... | 09/09/2008 |
| 7415087 | Circuits with state circuitry having cross connected control inputs Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or sync... | 08/19/2008 |
| 7415559 | Data processing systems and method for processing work items in such systems Described is a method for processing work items in a data processing system. An interrupt is generated in response to receipt of a work item on a queue and the generated interrupt is serviced to schedule a task by placing the task on a task queue for later processin... | 08/19/2008 |
| 7409483 | Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to proper... | 08/05/2008 |
| 7383587 | Exception handling control in a secure processing system A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain.... | 06/03/2008 |
| 7380041 | Managing input/output interruptions in non-dedicated interruption hardware environments Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. Th... | 05/27/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7373446 | Method and system for dynamically patching an operating system's interrupt mechanism In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the hos... | 05/13/2008 |
| 7363407 | Concurrent arbitration of multidimensional requests for interrupt resources The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an in... | 04/22/2008 |
| 7363411 | Efficient system management synchronization and memory allocation A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may ... | 04/22/2008 |
| 7360253 | System and method to lock TPM always ‘on’ using a monitor A computer may be secured from attack by including a trusted environment used to verify a known monitor. The monitor may be used to determine a state of the computer for compliance to a set of conditions. The conditions may relate to terms of use, such as credits av... | 04/15/2008 |
| 7355966 | Method and system for minimizing disruption in common-access networks A method and fibre channel switch element is provided for isolating a defective device that is coupled to a fibre channel arbitrated loop. The method includes, isolating a port if a loop initialization primitive (“LIP”) is detected from a device coupled to the a... | 04/08/2008 |
| 7356817 | Real-time scheduling of virtual machines A method for scheduling a plurality of virtual machines includes: determining a resource requirement (Xi) for each virtual machine (VM); determining an interrupt period (Yi) for each VM; and scheduling the plurality of VMs based, at least in pa... | 04/08/2008 |
| 7353531 | Trusted computing environment A trusted computing environment 100, wherein each computing device 112 to 118 holds a policy specifying the degree to which it can trust the other devices in the environment 100. The policies are updated by an assessor 110 which re... | 04/01/2008 |
| 7350006 | System and method of interrupt handling A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least importa... | 03/25/2008 |
| 7350007 | Time-interval-based system and method to determine if a device error rate equals or exceeds a threshold error rate An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a processor. The interrupt handler executes, upon expiration of a time period, ... | 03/25/2008 |
| 7340167 | Fibre channel transparent switch for mixed switch fabrics A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel switch element includes a first port that communicates with the targe... | 03/04/2008 |
| 7339823 | Nonvolatile semiconductor storage apparatus and method of driving the same A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses... | 03/04/2008 |
| 7340740 | Cooperatively multitasking in an interrupt free computing environment Multitasking in a hardware interrupt free environment. Event indicators are employed to multitask between processes of the environment. Processes to be multitasked register with one another, and then during processing, one of the processes toggles an event indicator... | 03/04/2008 |
