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"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 8108582 | Notifying asynchronous events to a host of a data storage system and apparatus for the same A method of notifying asynchronous events to a host of a data storage system is presented. The method comprises the steps of: detecting an asynchronous event; generating an interrupt message in response to the detected asynchronous event; and communicating the gener... | 01/31/2012 |
| 8074005 | Data processor and control system Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a... | 12/06/2011 |
| 8055827 | Guest interrupt controllers for each processor to aid interrupt virtualization In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to... | 11/08/2011 |
| 8037227 | System and method for virtualizing processor and interrupt priorities Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is prefer... | 10/11/2011 |
| 8028114 | Information processing apparatus, method, and program for simplifying an interrupt process The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S52 that a network card poin... | 09/27/2011 |
| 8024504 | Processor interrupt determination Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targe... | 09/20/2011 |
| 8019922 | Interruption facility for adjunct processor queues Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queu... | 09/13/2011 |
| 8001308 | Method and system for handling a management interrupt event in a multi-processor computing device A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered pr... | 08/16/2011 |
| 7996594 | Interrupt-driven link status feedback mechanism for embedded switches A computer implemented method, a tangible computer readable medium, and a data processing system intelligently propagate link status information received by a blade server to the various ports of an embedded multi-port switch. The link status of a switch port in an ... | 08/09/2011 |
| 7996593 | Interrupt handling using simultaneous multi-threading Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logi... | 08/09/2011 |
| 7987307 | Interrupt coalescing control scheme In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt ... | 07/26/2011 |
| 7979618 | Image forming apparatus and control method thereof An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt rou... | 07/12/2011 |
| 7930457 | Channel mechanisms for communicating with a processor event facility Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with pro... | 04/19/2011 |
| 7917677 | Smart profiler A method, system, and computer usable program product for a smart profiler are provided in the illustrative embodiments. An allowable number of interrupts for use by a profiler application is determined. A count number for a counter is determined. The counter is con... | 03/29/2011 |
| 7895382 | Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events a... | 02/22/2011 |
| 7886101 | Interruption control system and method An interruption control system includes two sense elements, a microprocessor, and a controller. The microprocessor includes two registers, two flip-latches, a multiplexer, and a microcontroller. Each sense element senses a device and sends a sense signal. The corres... | 02/08/2011 |
| 7886100 | Information processing apparatus and SMI processing method thereof An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an S... | 02/08/2011 |
| 7886099 | Systems and methods for providing a personal computer with non-volatile system memory In some embodiments, a system comprises a system memory module and an access card. The system memory module connects to a memory bus on a motherboard for a personal computer, while the access card connects to an expansion bus. The access card couples to the system m... | 02/08/2011 |
| 7873769 | Micro controller unit (MCU) capable of increasing data retention time and method of driving the MCU A method of operating a micro controller unit including maintaining a stop mode operation when a battery level detected in response to a first interrupt signal input from an external source is in a predetermined low voltage level range during the stop mode operation... | 01/18/2011 |
| 7853743 | Processor and interrupt controlling method A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a ... | 12/14/2010 |
| 7822899 | Data processor and control system Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a... | 10/26/2010 |
| 7809875 | Method and system for secure communication between processor partitions A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message. ... | 10/05/2010 |
| 7805555 | Multiprocessor system The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt... | 09/28/2010 |
| 7802042 | Method and system for handling a management interrupt event in a multi-processor computing device A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered pr... | 09/21/2010 |
| 7797473 | System for executing system management interrupts and methods thereof An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler, a second processor device of the information handling system can cont... | 09/14/2010 |
| 7793024 | Method for utilizing a PCI-Express bus to communicate between system chips A method for command transmission between systems is introduced. The command transmission between the systems, such as a north bridge chip, a south bridge chip and a central processing unit (CPU), employs the signals transmission specified by a PCI Express bus origi... | 09/07/2010 |
| 7761637 | Slave device with latched request for service Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to re... | 07/20/2010 |
| 7743193 | Logic gateway circuit for bus that supports multiple interrupt request signals A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output signal, an inverter having an input terminal connected to the interr... | 06/22/2010 |
| 7721033 | Interrupt notification block An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface port. The interrupt notification block is written by the host interface ... | 05/18/2010 |
| 7716407 | Executing application function calls in response to an interrupt Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represent... | 05/11/2010 |
| 7711881 | Method for restoring system configuration information of a network attached storage A method for restoring system configuration information of a network attached storage includes the steps of: setting system configuration information of an network attached storage as a backup file; registering an interrupt handler; pressing down an input key (16... | 05/04/2010 |
| 7702835 | Tagged interrupt forwarding A system for tagged interrupt forwarding comprises a multiprocessor including a first and a second processor, an I/O device, and I/O management software. In response to an application I/O request, the I/O management software may be configured to prepare a request de... | 04/20/2010 |
| 7694055 | Directing interrupts to currently idle processors Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which process... | 04/06/2010 |
| 7680972 | Micro interrupt handler A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt ... | 03/16/2010 |
| 7680973 | Sideband signal for USB with interrupt capability The invention provides for a sideband signal for the USB that has real-time interrupt capabilities. A system and method for hardware detection of an interrupt signal provides for the ability to superimpose a high frequency interrupt signal on a USB power line for tr... | 03/16/2010 |
| 7657683 | Cross-thread interrupt controller for a multi-thread processor An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, ... | 02/02/2010 |
| 7644214 | Information processing apparatus and task execution method An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned... | 01/05/2010 |
| 7624215 | Interrupt controller An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry is ... | 11/24/2009 |
| 7617345 | Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, where... | 11/10/2009 |
| 7613860 | Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, where... | 11/03/2009 |
