Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7966432 | Data processing device adaptable to variable external memory size and endianess A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising ... | 06/21/2011 |
| 7930445 | Computer system using remote I/O and I/O data transfer method To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the devic... | 04/19/2011 |
| 7877524 | Logical address direct memory access with multiple concurrent physical ports and internal switching A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides rando... | 01/25/2011 |
| RE41904 | Methods and apparatus for providing direct memory access control Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. V... | 10/26/2010 |
| 7783793 | Handling DMA operations during a page copy A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that in... | 08/24/2010 |
| 7774514 | Method of transmitting data between storage virtualization controllers and storage virtualization controller designed to implement the method A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a ... | 08/10/2010 |
| 7739423 | Bulk transfer of information on network device A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engin... | 06/15/2010 |
| 7702826 | Method and apparatus by utilizing platform support for direct memory access remapping by remote DMA (“RDMA”)-capable devices An apparatus and method related to performing Remote Direct Memory Access Request (“RDMA”) is presented. In one embodiment, the apparatus comprises Remote direct memory access (“RDMA”) logic that executes a direct memory access (“DMA”) request from the r... | 04/20/2010 |
| 7650440 | Peripheral supplied addressing in a simple DMA module A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller;... | 01/19/2010 |
| 7533198 | Memory controller and method for handling DMA operations during a page copy A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that in... | 05/12/2009 |
| 7467239 | Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying th... | 12/16/2008 |
| 7444441 | Device including means for transferring information indicating whether or not the device supports DMA A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... | 10/28/2008 |
| 7426588 | Storage apparatus In a data input/output with other apparatus, a data transfer controller (DTC) of a storage controller multiprocesses a data transfer with the other apparatus by utilizing a saving/recovering operation and suppresses a load therefrom, thereby improving performance th... | 09/16/2008 |
| 7415550 | System and method for controlling DMA data transfer A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transf... | 08/19/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7380115 | Transferring data using direct memory access A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the prima... | 05/27/2008 |
| 7373437 | Multi-channel DMA with shared FIFO A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (... | 05/13/2008 |
| 7370137 | Inter-domain data mover for a memory-to-memory copy engine Address translation for a source and destination of the data that utilizes different page tables. A direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a page-table walk and address translation for a source side of the copy, and ... | 05/06/2008 |
| 7370150 | System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7356630 | Processor control device for stopping processor operation A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module,... | 04/08/2008 |
| 7356621 | Method and system for transferring data between a requesting program and a hardware device Transferring data between a requesting program and a hardware device. An program requests a pre-allocation of non-pageable memory. The program requests a transfer via a direct memory access (DMA) from the hardware device into the non-pageable memory. The requesting ... | 04/08/2008 |
| RE40213 | Methods and apparatus for providing direct memory access control Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. V... | 04/01/2008 |
| 7343515 | System and method for performing error recovery in a data processing system having multiple processing partitions A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partitio... | 03/11/2008 |
| 7343434 | Buffer management within SLS (simple load store) apertures for inter-endpoint communication in advanced switching fabric A single copy memory sharing scheme between multiple endpoints in an interconnect architecture may use a buffer management method in an advanced switching fabric having multiple endpoints that divides a simple load and store memory aperture into a buffer descriptor ... | 03/11/2008 |
| 7334108 | Multi-client virtual address translation system with translation units of variable-range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 02/19/2008 |
| 7318149 | Semi-persistent relocatable ram-based virtual floppy disk method A method and related structure for providing operating system drivers during installation of the operating system, where those operating system drivers are provided by way of a virtual disk drive. Basic input/output system (BIOS) routines are adapted to support show... | 01/08/2008 |
| 7318090 | Method for utilizing concurrent context switching to support isochronous processes A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading pr... | 01/08/2008 |
| 7318174 | Systems, methods, and computer readable medium for analyzing memory Techniques are provided for expanding the functionality of live memory analysis commands to analyze a memory dump or other differing memory types. To this end, a live memory command which normally analyzes live memory is modified to invoke a virtual machine. Live me... | 01/08/2008 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7305403 | Method and device for storing linked lists The invention provides for a method, a device, a use of the method and a computer program, all of which increase the security of linked lists for the storage of data. This is achieved by an improved protection against the destruction of data caused by defective poin... | 12/04/2007 |
| 7302546 | Method, system, and article of manufacture for reserving memory Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wher... | 11/27/2007 |
| 7302699 | Logged-in device and log-in device A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous lo... | 11/27/2007 |
| 7296139 | In-memory table structure for virtual address translation system with translation units of variable range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 11/13/2007 |
| 7293155 | Management of access to data from memory Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of d... | 11/06/2007 |
| 7293120 | DMA module having plurality of first addressable locations and determining if first addressable locations are associated with originating DMA process A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory location. The address counter does not act on an internal register of the DM... | 11/06/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7287101 | Direct memory access using memory descriptor list Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list that references the pages allocated to the buffer. A direct memory acce... | 10/23/2007 |
